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UCC3911 -1/-2/-3/-4
PRELIMINARY
Lithium-Ion Battery Protector
FEATURES
* Protects Sensitive Lithium-Ion Cells from Overcharging and Over-Discharging * Used for Two-Cell Lithium-Ion Battery Packs * No External FETs Required * Provides Protection Against Battery Pack Output Short Circuit * Extremely Low Power Drain on Batteries of About 20A * Low Internal FET Switch Voltage Drop * User Controllable Delay for Tripping Short Circuit Current Protector * 3A Current Capacity
BLOCK DIAGRAM
UDG-95130-2
DESCRIPTION
The UCC3911 is a two-cell lithium-ion battery pack protector IC that incorporates an on-chip series FET switch thus reducing manufacturing costs and increasing reliability. The IC's primary function is to protect both lithium-ion cells in a two-cell battery pack from being either overcharged or over-discharged. It employs a precision bandgap voltage reference that is used to detect when either cell is approaching an overcharged or over-discharged state. When on board logic detects either condition, the series FET switch opens to protect the cells. A negative feedback loop controls the FET switch when the battery pack is in either the overcharged or over-discharged state. In the overcharged state the action of the feedback loop is to allow only discharge current to pass through the FET switch. In the over-discharged state, only charging current is allowed to flow. The op amp that drives the loop is powered only SLUS429 - DECEMBER 1999 when in one of these two states. In the over-discharged state the chip enters sleep mode until it senses that the pack is being charged. The FET switch is driven by a charge pump when the battery pack is in a normally charged state to achieve the lowest possible RDSON. In this state the negative feedback loop's op amp is powered down to conserve battery power. Short circuit protection for the battery pack is provided and has a nominal delay of 100s before tripping. An external capacitor may be connected between CDLY and B0 to increase this delay time to allow longer overcurrent transients. A chip enable (CE) pin is provided that while held low, inhibits normal operation of the chip to facilitate assembly of the battery pack. The UCC3911 is specified for operation over the temperature range of -20C to +70C, the typical operating and storage temperature range of lithium-ion batteries.
UCC3911 -1/-2/-3/-4
ABSOLUTE MAXIMUM RATINGS
Maximum Input Voltage (B2, GND) . . . . . . . . . . . . . . . . . . . 14V Minimum Input Voltage (B0, GND) . . . . . . . . . . . . . . . . . . -9.0V Maximum Charge Current (B0, GND) . . . . . . . . . . . . . . . . 3.3A Minimum Discharge Current (B0, GND) . . . . . . . . . . . . . . . 3.3A Storage Temperature . . . . . . . . . . . . . . . . . . . -65C to +150C Junction Temperature . . . . . . . . . . . . . . . . . . . -55C to +150C Lead Temperature (Soldering, 10 sec.) . . . . . . . . . . . . . +300C
CONNECTION DIAGRAM
SOIC-16 (Top View) DP Package
Currents are positive into, negative out of the specified terminal. Consult Packaging Section of Databook for thermal limitations and considerations of packages.
ELECTRICAL CHARACTERISTICS: Unless otherwise specified, these specifications apply for -20C to +70C for the UCC3911, all voltages are referenced to B0, VB2 = 7.2V, TA = TJ.
PARAMETER State Transition Threshold Normal to Overcharge Overcharge to Normal Normal to Overcharge Overcharge to Normal Normal to Overcharge Overcharge to Normal Normal to Overcharge Overcharge to Normal Normal to Undercharge Undercharge to Normal B0/GND Switch VB0 - VGND (Normal) IGND = 2A (Normal) IGND = -2A (Overcharge) IGND = 1mA (Overcharge) IGND = 2A (Undercharge) IGND = -1mA (Undercharge) IGND = -2A IGND Chip Bias Current IB2 IB2 IB1 Nominal In Sleep Mode -1 18 3.5 0 1 25 A A A (Overcharge) VGND = -5V (Undercharge) VGND = 5V -5 0 30 -300 -500 -320 -160 160 -150 -250 150 250 300 500 320 mV mV mV mV mV mV A A UCC3911-4 UCC3911-3 UCC3911-2 UCC3911-1 4.15 3.6 4.2 3.65 4.25 3.7 4.3 3.75 2.42 2.90 4.2 3.7 4.25 3.75 4.3 3.8 4.35 3.85 2.5 3.0 4.25 3.8 4.3 3.85 4.35 3.9 4.4 3.95 2.58 3.10 V V V V V V V V V V TEST CONDITIONS MIN TYP MAX UNITS
2
UCC3911 -1/-2/-3/-4
ELECTRICAL CHARACTERISTICS: Unless otherwise specified, these specifications apply for -20C to +70C for the UCC3911, all voltages are referenced to B0, VB2 = 7.2V, TA = TJ.
PARAMETER Short Circuit Protection ITHRESHOLD TDLY Internal Clock Frequency TDLY - OV TDLY - UV OV, UV Output Characteristics Thermal Shutdown KILL Output Characteristics KILL Output Characteristics LPWARN Output Characteristics CE Threshold Voltage CDLY = Open (Note 1) (Note 2) Delay for Chip to Register OV Condition Delay for Chip to Register UV Condition VB2 - VHIGH with IPIN = -100A VLOW With IPIN = 100A (Note 1) VB2 - VHIGH With IKILL = -0.5mA VLOW With IKILL = 0.5mA VB2 - VHIGH With ILPWARN = -0.1mA VLOW With ILPWARN = 0.1mA VB2 = 8.5V VDD = 5V 5 2.05 0.6 0.3 3.5 5.25 100 7.5 2 1 0.15 0.05 165 0.075 0.05 0.05 0.04 6 2.45 0.290 0.27 0.42 0.37 7 4.05 5 3.5 0.50 0.43 7 A
s
TEST CONDITIONS
MIN
TYP
MAX UNITS
kHz ms ms V V C V V V V V V
Note 1: Guaranteed by design. Not 100% tested in production. Note 2: Tested at functional probe only.
PIN DESCRIPTIONS
B0: Connects to the negative terminal of the lower cell in the battery pack. B1: Connects to the junction of the positive terminal of the lower cell and the negative terminal of the upper cell in the battery pack. B2: Connects to the positive terminal of the upper cell in the battery pack. This pin also connects to the positive of the two terminals that are presented to the user of the battery pack. CDLY: Delay control pin for the short circuit protection feature. A capacitor connected between this pin and the B0 pin will lengthen the time delay from when an overcurrent situation is detected to when the protection circuitry is activated. This control will be useful for those applications where high peak load currents may momentarily exceed the protection circuit's threshold current and interruption of the battery current would be undesirable. The nominal delay time is internally set at 100s. The equation for determining this delay is: TDLY (s) = 25 + (25 + CDLY (pF)) * 0.4 * VB2 To recover from an overcurrent "shutdown" the load must be removed momentarily from the pack. 3 CE: Chip Enable. While this signal is held low, the internal FET is held off and the KILL latch is held in reset. CE is pulled high by a 2A current source. This function was included to facilitate construction of the battery pack by preventing the KILL latch from being erroneously set during final assembly. The last step in the electrical assembly of the pack would be cutting a link to B0. GND: The second of the two terminals that are presented to the user of the battery pack. The internal FET switch connects this terminal to the B0 terminal to give the battery pack user appropriate access to the batteries. In an overcharged state, current is allowed to flow only into this terminal. Similarly, in an over-discharged state, current is allowed to flow only out of this terminal. KILL: This active-high signal indicates that one or both of the cells has been overcharged. It can be used to drive a circuit breaker of some sort to permanently disable the battery pack as a safety feature. Note that when KILL goes active the chip simultaneously enters the OV state which inhibits further charging of the pack. The KILL latch is asynchronously reset by the CE signal.
UCC3911 -1/-2/-3/-4
LPWARN: This active-high signal is the low Power Warning. The voltage on this pin goes high (to B2 potential) as soon as either of the battery's cells voltage falls below 3.0V. Once the UV state is entered, this output goes back to low. OV: This active-low signal indicates the state of the state machine's OV bit. When low, it indicates that one or both cells are overcharged. Further charging is inhibited by the opening of the FET switch. The internal signal also sets the KILL latch and activates the KILL output signal. The output buffer for this pin is sized to drive a very light load. SUBS: The substrate connections for the UCC3911. Connect these points to a heat sink which is electrically isolated from all other IC pins. UV: This active-low signal indicates the state of the state machine's UV bit. When low, it indicates that one or both cells are over- discharged. Further discharging is inhibited by the opening of the FET switch. The chip enters the "Sleep" mode when UV goes high and waits in this state until the chip detects that the battery pack has been placed in a charging circuit. The output buffer for this pin is likewise sized to drive a very light load.
APPLICATION INFORMATION
PACK+
UCC3911 B2 C3 0.1F 25V 1 2 ISOLATED COPPER PAD FOR HEAT SINKING AT HIGH LOAD CURRENTS 3 4 5 6 PACK- 7 8 LOW POWER WARN (ACTIVE HIGH) KILL CDLY 330pF OV UV SUBS SUBS GND GND LPWARN CDLY B1 SUBS SUBS B0 B0 CE 15 16
R1 220
C1 10F 10V R1 10k
+
CELL 2 + C4 (OPTIONAL)
14 13 12 11 10 9 J1 ENABLE (OPEN) ISOLATED COPPER PAD FOR HEAT SINKING AT HIGH LOAD CURRENTS C2 0.22F
+
CELL 1
Note: In this example, CDLY, C1 and C2 were selected to drive a 1500F load.
UDG-99173
Figure 1. UCC3911 Application circuit including components for short circuit protection.
Figure 1 shows a typical application for the UCC3911 lithium-ion battery protector. All of the functions required to protect two series lithium-ion cells from overcharge and over-discharge, as well as provide short circuit protection, are included in a single chip. An internal state machine controls an internal power FET which allows either bi-directional or uni-directional battery current. An optional 4
time delay capacitor can be included to slow the reaction time of the short circuit protection circuitry if desired. While the IC is capable of providing overload and over/undervoltage protection of both cells with virtually no external parts, the demands of true short circuit protection require some passive external components.
UCC3911 -1/-2/-3/-4
APPLICATION INFORMATION (cont.)
State Machine Operation The internal state machine constantly monitors the two cells for both overvoltage and undervoltage conditions. Figure 2 shows a state diagram which describes the operation of the protection circuitry. In the normal mode, both the OV and UV status bits are held high and full battery current is allowed through the internal power FET in either the charge or discharge direction. If the voltage across one or both cells falls below 2.5V, the UV signal goes low, and the feedback loop allows only charge current. The LPWARN signal goes low and the UCC3911 enters sleep mode which consumes only 3 A, limiting self discharge to a minimum. The circuit remains in this state until the voltage across both cells exceeds 3V. The battery pack can still be charged, unless the sum of the two cells voltages falls below 3.7V, which is the minimum guaranteed operating voltage for the IC. If the battery cells become so poorly matched that the voltage across one cell exceeds 4.25V and the voltage across the other cell falls below 2.5V, the power FET will not pass either charge or discharge current, and both the OV and UV signals will be set low. The normal high current path for battery current is through the B0 (10, 11) and GND (6, 7) pins of the UCC3911. The GND pins are intended to be connected to system ground for either the charger or the load. The SUBS pins (4, 5, 12, 13) are internally connected to the substrate of the UCC3911, which is internally referenced to B0 or GND depending on the direction of pack current. If high battery currents are anticipated, the SUBS pins can be thermally connected to a heat sink to control the IC temperature. However, this heat sink must be electrically isolated from all other IC pins including ground. This is a critically important point, as heat sinking to the system ground is not possible. The CE pin is used to initialize the state of the battery pack during assembly. Holding this pin low forces the state machine to hold the FET off. The last step in the assembly process would be to cut the trace between this pin and B0 which allows the internal pull up to start the state machine. Short Circuit Protection As stated earlier, the demands of true short circuit protection requires that careful attention be paid to the selection of a few external components. This selection is discussed below. In the Application circuit of Fig. 1, C3 protects the battery pack output terminals from inductive kick when the pack current is shut off due to an overcurrent or over/undervoltage condition. (It also increases the ESD protection level.) To prevent a momentary cell voltage drop, caused by large capacitive loads, from causing an erroneous undervoltage shutdown, an RC filter is required in series with the two battery sense inputs, B1 and B2. The resistors (R1 and R2) are sized to have a negligible impact on voltage sensing accuracy. The capacitors (C1 and
UDG-96122
Note: The "One Cell Over and One Cell Under" state is entered whenever one cell is overcharged and the other cell is simultaneously over-discharged. When in this state, the series FET switch is turned off inhibiting both charging and discharging of the battery pack. If the battery pack ever gets into this condition, it should be discarded.
Figure 2. State diagram.
If the voltage across one or both cells exceeds 4.25V, the OV signal goes low, and further charge current is not allowed. An internal feedback loop controls the power FET to allow only discharge current, allowing for battery recovery. The state machine will not reenter normal mode until the voltage across both cells decays to less than 3.75V. This feature is important to prevent circuit oscillation due to battery ESR when the circuitry transitions between states. The KILL output signal is also set high when the UCC3911 enters the OV state, and will remain set unless the CE pin is brought low. The KILL latch can be used to permanently disable the battery pack with additional circuitry if desired. If the voltage across one or both battery cells falls below 3V, the LPWARN signal goes high indicating a low power condition. This signal can be used to signal the user that the battery pack is in need of charge.
5
UCC3911 -1/-2/-3/-4
APPLICATION INFORMATION (cont.)
C2) should be sized to provide a time constant longer than the overcurrent delay time. In the example of Figure 1, they are sized for a nominal 2.2ms time constant. They do not need to be low ESR style capacitors, as they see no ripple current. A larger resistor value and smaller capacitor value can be used on the B1 input due to the extremely low input current on this pin. The overcurrent delay capacitor, CDLY, sets the time delay, after the overcurrent threshold is exceeded, before turning off the UCC3911's internal FET. If no capacitor is used, the nominal delay is 100 s. To charge large capacitive loads without tripping the overcurrent circuit, a small capacitor (typically less than 1000pF) is used to extend the delay time. The approximate delay time is given below and shown graphically in Figure 3. (5.25A nominal), and V is the battery voltage. Using the minimum trip current of 3.5A and the maximum battery voltage of 8.4V, the worst case maximum delay time required is defined as: R t max (s ) = -R * C (F ) * 1n * . 24 In the example of Figure 1, CDLY, C1 and C2 are sized to drive a 1500 F load capacitor. If large capacitive loads (or other loads with surge currents above the overcurrent trip threshold) are not being applied to the pack terminals, the overcurrent delay time can be short. In this case, it may be possible to eliminate CDLY, as well as R2 and C2 altogether (replacing R2 with a short). In addition, the time constant of R1 and C1 can be made much shorter. R1 and C2 are still necessary, however, to assure proper operation under short circuit conditions. It is important to maintain a minimum R1/C1 time constant of 100 s. (For example, R1 and C1 could be reduced to 100 and 1 F.) Capacitor C4 is recommended, for the case where the wires connecting to the top and bottom of the cell stack are more than an inch long (not likely in a small battery pack). In this case, a 10 f, low ESR capacitor is recommended to prevent excessive overshoot at turn-off due to wiring inductance.
t DLY (s ) = 25 + (25 + C DLY ( pF )) * 0.4 * V B 2
The amount of time required will be a function of the load capacitance, battery voltage, and the total circuit impedance, including the internal resistance of the cells, the UCC3911's on resistance, and the load capacitor ESR. The required delay time can be calculated from: I *R t = -R * C * 1n V In this equation, R is the total circuit resistance, C is the capacitor being charged, I is the overcurrent trip current
3,500 3,000 2,500 DELAY (us) 2,000 1,500 1,000 500 0 0 200 400 600 DELAY CAP (pF) 800
VB2 = 8 VB2 = 7 VB2 = 6 VB2 = 5
1,000
UNITRODE CORPORATION 7 CONTINENTAL BOULEVARD * MERRIMACK, NH 03054 TEL (603) 424-2410 ( FAX (603) 424-3460
Figure 3. Nominal overcurrent delay time vs CDLY and B2 voltage.
6
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