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OCX256 Crosspoint Switch
Advanced Datasheet
Features
667 Mb/s port data bandwidth, >85Gb/s aggregate bandwidth Low power CMOS, 2.5V and 3.3V power supply SRAM-based, in-system programmable LVDS I/O (OCX256L) and LVPECL I/O (OCX256P) versions * 256 configurable I/O ports - 128 dedicated differential input ports - 128 dedicated differential output ports - LVTTL control interface - Output Enable control for all outputs * Non-blocking switch matrix - Patented ActiveArrayTM matrix for superior performance - Double-buffered configuration RAM cells for simultaneous global updates - ImpliedDisconnectTM function for single cycle disconnect/ connect * * * * * Full Broadcast and multicast capability - One-to-One and One-to-Many connections - Special broadcast mode routes one input to all outputs at maximum data rate * Registered and flow-through data modes - 333 MHz synchronous mode - 667 Mb/s asynchronous mode - Low jitter and signal skew - Low duty cycle distortion * RapidConfigureTM parallel interface for configuration and readback * JTAG serial interface for configuration and Boundary Scan testing * 792 TBGA package with 1.00mm ball spacing * Integrated Termination Resistors
Description
The OCX256 SRAM-based devices are non-blocking 128 X 128 digital crosspoint switches and are available in LVDS (Low Voltage Differential Signaling) and LVPECL (Low Voltage PECL) versions. Both devices are capable of data rates of 667 Megabits per second per port. The I/O ports are fixed as either input or output ports. The input ports support flow-through mode only. The output ports are individually programmable to operate in either flow-through (asynchronous) or registered (synchronous) mode. Each output register may be clocked by a global clock or a next neighbor clock source. The patented ActiveArray provides greater density, superior performance, and greater flexibility compared to a traditional n:1 multiplexer architecture. The OCXTM devices support various operating modes covering one input to one output at a time as well as one input to many outputs, plus a special broadcast mode to program one input to all outputs while maintaining maximum data rates. In all modes data integrity and connections are maintained on all unchanged data paths. The RapidConfigure parallel interface allows fast configuration of both the Output Buffers and the switch matrix. Readback is supported for device test and verification purposes. The OCX256 also supports the industry standard JTAG (IEEE 1149.1) interface for boundary scan testing. The JTAG interface can also be used to download configuration data to the device and readback data. A functional block diagram of the OCX256 is shown in Figure 1.
Applications
* SONET/SDH and DWDM * Digital Cross-Connects
256 IN[127:0] Input Buffers 128 x 128 Crosspoint Switch Matrix
* System Backplanes and Interconnects * High Speed Test Equipment
256 OUT[127:0] Output Buffers
* ATM Switch Cores * Video Switching
2 CLK OE#
RapidConfigure Signals
RCA[6:0] 7 RCB[6:0] 7 RCI[3:0] 4 RCO[4:0] 5 RC_CLK# RC_EN# UPDATE# Configuration and Programming Logic
TCK TMS TDI TRST# TDO HW_RST#
JTAG Signals
Figure 1 OCX256 Functional Block Diagram Fairchild Semiconductor [Rev. 2.0] 3/21/02 1
OCX256 Crosspoint Switch--Advanced Datasheet
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OCX256 Crosspoint Switch--Advanced Datasheet
Contents
1. 1.1 Introduction ........................................................................................................................... 7 Input and Output Buffers...................................................................................................... 8 Input and Output Port Function Mode ........................................................................... 8 Broadcast Mode ............................................................................................................. 9
1.1.1 1.1.2 1.2
Output Buffer Configuration ................................................................................................ 9 Output Control Signals................................................................................................... 9 Neighboring Output Port as a Clock Source .................................................................. 9
1.2.1 1.2.2 1.3
RapidConfigure Interface ....................................................................................................11 RapidConfigure Programming Instructions.................................................................. 11
1.3.1 1.4
JTAG Configuration Controller.......................................................................................... 14 JTAG Interface............................................................................................................. 14 Output Port Configuration ........................................................................................... 14 Switch Matrix Configuration ....................................................................................... 14 Mode Control Register Configuration.......................................................................... 14 JTAG Architecture and Shift Registers ........................................................................ 15 JTAG State Machine .................................................................................................... 16 JTAG Input Format ...................................................................................................... 16 JTAG Instructions ........................................................................................................ 17
1.4.1 1.4.2 1.4.3 1.4.4 1.4.5 1.4.6 1.4.7 1.4.8 1.5 1.6 2. 3. 3.1 3.2 4. 4.1 4.2 4.3 4.4
ImpliedDisconnect ............................................................................................................. 19 Device Reset Options ......................................................................................................... 20 Pin Description .....................................................................................................................21 Differential I/O Standards ...................................................................................................22 LVDS ................................................................................................................................. 22 LVPECL ............................................................................................................................. 23 Electrical Specifications .......................................................................................................24 Absolute Maximum Ratings .............................................................................................. 24 Recommended Operating Conditions ................................................................................ 24 Pin Capacitance ................................................................................................................. 24 DC Electrical Specifications .............................................................................................. 25
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OCX256 Crosspoint Switch--Advanced Datasheet
4.5 4.6 5. 5.1 5.2 5.3 5.4 5.5 6. 6.1 6.2 7. 8. 9. AC Electrical Specifications............................................................................................... 26 Timing Diagrams................................................................................................................ 27 Package and Pinout ............................................................................................................. 31 Package Pinout ................................................................................................................... 31 Pinout by Ball Sequence..................................................................................................... 32 Pinout by Ball Name .......................................................................................................... 36 Package Dimensions........................................................................................................... 40 Package Thermal Characteristics........................................................................................ 42 Power Consumption ............................................................................................................ 43 Power for OCX256L (LVDS) ............................................................................................ 43 Power for OCX256P (LVPECL) ........................................................................................ 44 Component Availability and Ordering Information ......................................................... 45 Glossary ................................................................................................................................ 45 Product Status Definition .................................................................................................... 47
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Figures
Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 Figure 21 OCX256 Functional Block Diagram .................................................................................................... 1 OCX256 Switch Matrix ........................................................................................................................ 7 Input and Output Buffer Configuration ................................................................................................ 8 Next Neighbor Clock Block Diagram ................................................................................................ 10 OCX256 JTAG Architecture .............................................................................................................. 15 OCX256 JTAG State Machine ........................................................................................................... 16 OCX256L LVDS Signal Circuit......................................................................................................... 22 OCX256P LVPECL Signal Circuit .................................................................................................... 23 Registered Output Mode Timing ........................................................................................................ 27 Flow-Through Mode Timing .............................................................................................................. 27 Output Enable Timing ........................................................................................................................ 27 Duty Cycle Distortion ......................................................................................................................... 28 RapidConfigure Write Cycle .............................................................................................................. 28 RapidConfigure Read Cycle ............................................................................................................... 29 JTAG Timing ...................................................................................................................................... 29 Typical Performance at 667 Mb/s with PRBS Data ........................................................................... 30 OCX256 Package Pinout .................................................................................................................... 31 OCX256 Package--Bottom View ...................................................................................................... 40 OCX256 Package--Top and Side Views ........................................................................................... 41 Power Consumption Diagram for the OCX256L using LVDS .......................................................... 43 Power Consumption Diagram for the OCX256P using LVPECL...................................................... 44
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OCX256 Crosspoint Switch--Advanced Datasheet
Tables
Table 1
Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Table 17 Table 18 Table 19 Table 20 Table 21 Table 22
Summary for Programmable I/O Attributes for OCX256 ................................................................. 8
Next Neighbor Outputs.................................................................................................................... 10 RapidConfigure Programming Instructions .................................................................................... 11 RCO[4:0] Readback Pin Assignment.............................................................................................. 13 Programming an Output Buffer using RapidConfigure .................................................................. 13 Mode Control Register .................................................................................................................... 14 JTAG Input Format ......................................................................................................................... 16 JTAG Instructions ........................................................................................................................... 17 Programming an Output using JTAG.............................................................................................. 19 Number of JTAG Cycles and Configuration Time ......................................................................... 19 Device Reset Options ...................................................................................................................... 20 OCX256 Pin Description................................................................................................................. 21 Absolute Maximum Ratings1.......................................................................................................... 24 Recommended Operating Conditions.............................................................................................. 24 Pin Capacitance5 ............................................................................................................................. 24 LVTTL DC Electrical Specifications.............................................................................................. 25 OCX256L (LVDS) DC Electrical Specifications (VDD.PAD = 2.5V) ............................................ 25 OCX256P (LVPECL) DC Electrical Specifications (VDD.PAD = 3.3V)........................................ 25 AC Electrical Specifications............................................................................................................ 26 OCX256 Pinout By Ball Sequence.................................................................................................. 32 OCX256 Pinout By Ball Name ....................................................................................................... 36 Package Thermal Coefficients......................................................................................................... 42
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OCX256 Crosspoint Switch--Advanced Datasheet 1. Introduction
The OCX256 is a differential crosspoint-switching device. The main functional block of the device is a Switch Matrix as shown in Figure 1. The Switch Matrix is a x-y structure supporting an input-to-output data flow. Figure 2 shows a conceptual view of the switch matrix with inputs connected to the horizontal trace and outputs to the vertical trace. Connections between vertical and horizontal lines are implemented with a proprietary highperformance buffering circuit. Signal path delays through the Switch Matrix are very well balanced, resulting in predictable and uniform pin-to-pin delays. Note - For the purpose of clarity, the logic diagrams within this datasheet are conceptual representations only and do not show actual circuit implementation.
Data
Loading SRAM Cell
Active SRAM Cell
UPDATE#
Proprietary High-performance Buffering Circuit
Figure 2
OCX256 Switch Matrix
The Active SRAM cells are responsible for establishing connections in the switch matrix by turning on the interconnect circuit, while the Loading SRAM cell can be used to store a second configuration that can be transferred to the Active SRAM cell at a later time. The two SRAM cells are arranged so that a double buffered scheme can be employed. Through the use of an internal signal (generated automatically during a programming cycle) it is possible to store a second configuration map in the Loading SRAM while the Active SRAM maintains its present connection status. When the UPDATE# signal is asserted low (# denotes active low), the contents of the Loading SRAM cell are transferred to the Active SRAM cell and the switch matrix connection is either made or broken. The UPDATE# signal can be used to control when the switch matrix is reconfigured. For instance, as long as the UPDATE# signal is de-asserted (held high), the Loading SRAM cells for the entire switch matrix could be changed without affecting the current configuration of the switch. When the UPDATE# signal is asserted low, the entire switch matrix would be reconfigured simultaneously. If the UPDATE# signal is asserted continuously, all crosspoint programming commands (generated by RapidConfigure or JTAG programming cycles) will take effect immediately, since the Loading SRAM cell's contents will be transferred directly to the Active SRAM cell.
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OCX256 Crosspoint Switch--Advanced Datasheet
1.1 Input and Output Buffers
All of the input buffers are differential inputs with flow-through mode. The output buffers are programmable for either flow-through or registered mode. Figure 3 shows the basic block diagram of the input and output blocks with the sources for the output control signals (OE# and CLK). The control signals are explained in more details in the following sections.
Output Mode Select Input Switch Matrix Output D Q
CLK Next Neighbor Clock Select
OE#
Figure 3
Input and Output Buffer Configuration
1.1.1 Input and Output Port Function Mode
The following legend describes the various modes of the Input and Output Ports and the specification used by the OCXProTM Software. Legend: Ax-Switch Matrix Signal Px-Port Signal OE#-Output Enable (# means "Active Low") CLK-Clock
Table 1 Symbol Px Ax Summary for Programmable I/O Attributes for OCX256 I/O Port Function Input - The external signal is buffered from the Input Port pin to the corresponding Switch Matrix line. Mnemonic IN
Ax
Px
Output - The internal signal is buffered from the corresponding Switch Matrix line to the Output Port pin. In this mode an optional output enable (OE#) can be selected. The default state is logic high with enable set to ON. Registered Output - The internal signal on the Switch Matrix line is registered by an edge-triggered register within the Output Port. A clock source is required in this mode. An output enable (OE#) is available but not required.
OP
OE# RO Ax CLK OE# Px Ax No Connect - In this mode, the output Port pin is isolated from the Switch Matrix. NC Px
D
Q
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1.1.2 Broadcast Mode
The OCX256 has a special Broadcast Mode which connects any input to all outputs without performance degradation. The input is selected using RapidConfigure or JTAG and disconnects all other inputs. The Global Update pin (UPDATE#) must be held high during Broadcast Mode. Asserting the UPDATE# pin returns the array to the previous program condition.
1.2 Output Buffer Configuration
Every output port of the OCX256 can be configured as either a flow-through or registered output. In registered mode there are two clock sources that are available:
* *
Global Clock Next Neighbor
Additionally, there are output control signals.
1.2.1
Output Control Signals
Every output port of the OCX has a global Output Enable signal (OE#). All output buffers have output enables that have programmable polarity and are individually configurable. Additionally each output can be permanently enabled (always ON) or disabled (always OFF) which is useful for applications which need to tri-state outputs (for example when using multiple chips in expansion mode) or for power saving in designs that do not need to use all the outputs available. Two control bits are used to control the function of the output enable function as described in Table 5.
1.2.2
Neighboring Output Port as a Clock Source
A physically adjacent port can be used as a clock source for an output port configured in registered mode. These outputs are grouped in pairs such that the signal being switched through OUT0 can be used to clock the signal being switched through OUT1, and vice versa. Any single clock or data input signal can be used to clock any other input signal provided they are switched to an appropriate output pair (see Table 2). Figure 4 shows the implementation of next neighbor output port clocking in the OCX256 switch. For example, INx is used for data input while INy is used for the corresponding clock. INx is connected to OUT0 via the crosspoint array while INy is connected to OUT1 via the crosspoint array. OUT0 is configured in registered output (RO) mode with OUT1 as its next neighbor clock selection. OUT1 will output the clock signal as well as clock the data in OUT0. Adjacent port selection is required for next neighbor clocking in the registered output mode. This feature is useful in many applications where different types of data switching through the crosspoint array have various associated clocks. To match the delays in the data and corresponding clocks, it is common practice to pass the clocks through the switch along with the data.
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OCX256 Crosspoint Switch--Advanced Datasheet
Crosspoint Array Any Input Port (INx) D CLK Next Neighbor Clock Select Q
Output Mode Select
OUT0
OE#
Output Mode Select Any Input Port (INy) D CLK Next Neighbor Clock Select OE# Q
OUT1
Figure 4
Next Neighbor Clock Block Diagram
The advantages of next neighbor clocking are: 1. Using next neighbor clocking in the registered output (RO) mode helps reduce the skew in outgoing data. 2. For a design with a large number of outputs switching simultaneously, next neighbor clocking mode is useful to stagger outputs for reduced board noise caused by simultaneous switching outputs. Note - Selecting the next neighbor clock for both outputs at the same time is not recommended. Only one output in the pair at a time can be clocked by its next neighbor.
Table 2 Next Neighbor Outputs
Pairing Sequence for Neighboring Outputs Output Next Neighbor Pairs 0,1 2,3 4,5 6,7 8,9 124,125 126,127
Only OUT1 can neighbor with OUT0, OUT3 with OUT2, etc. OUT2 cannot neighbor with OUT1, or OUT4 with OUT3, etc.
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1.3 RapidConfigure Interface
RapidConfigure (RC) is a 25 signal parallel interface that is used to program the OCX256 device. The 25 pins are allocated as follows: RCA[6:0] = RapidConfigure Address A. RCA are input pins. RCB[6:0] = RapidConfigure Address B. RCB are input pins. RCI[3:0] = RapidConfigure Instruction Bits RCO[4:0] = RapidConfigure Readback. RCO are output pins. RC_CLK# = RapidConfigure Clock RC_EN# = RapidConfigure Cycle Enable (state is sensed on negative edge of clock)
1.3.1
RapidConfigure Programming Instructions
The RC interface supports both write and read types of operations: 1. Write Operations (reset crosspoint and Input or Output Buffer (IOB), configure an Output Buffer, connect/disconnect crosspoint) 2. Read Operations (Output Buffer and crosspoint configuration read).
Table 3 RapidConfigure Programming Instructions RCO[4:0] Instruction Reserved Reserved X X Reset Crosspoint Array Reset, along with an Update operation (UPDATE# pin or Update command), resets the entire crosspoint array to no connect. All Output Buffers remain unchanged by this operation. Connects the input selected by RCB[6:0] to all output ports and disconnects all other inputs. The Global Update (UPDATE#) pin must be held high during Broadcast mode. Activating the Global Update pin returns the array to the previous program condition. Program an Output Buffer specified by RCA[6:0]. See Table 5 for RCB[6:0] bit assignment and buffer functionality. Description
RCI[3:0] 0000 0001 0010
RCA[6:0]
RCB[6:0]
0011
X
Input Port Address
Set Array to Broadcast mode
0100
Output Port Address
Data
Configure an Output Buffer
0101 Cycle 1 Output Port Address Input Port Address X
Readback Crosspoint, Output Buffer status
This is a two-cycle instruction. Specify the crosspoint connect status at output location specified by RCA[6:0] to the input location specified by RCB[6:0].
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OCX256 Crosspoint Switch--Advanced Datasheet
Table 3 RCI[3:0] Cycle 2 RCA[6:0] X RCB[6:0] X RapidConfigure Programming Instructions (Continued) RCO[4:0] Output Data Instruction Description Readback (using RCO[4:0]) the status of the output buffer specified in Cycle 1 by RCA[6:0], the output buffer specified in Cycle 1 by RCO[4:0] and the crosspoint connect status. See Table 4 for RCO[4:0] readback pin assignment. 0110 0111 X X X Input Port Address Input Port Address Update Disconnect Input Program the Global Update function without the use of the UPDATE# pin. Disconnect the crosspoint cells of the output row location specified by RCA[6:0]. Disconnect the crosspoint cell at the output location specified by RCA[6:0] to the input location specified by RCB[6:0]. All other connections from the source input address or to the same output address remain the same as before. 1001 Output Port Address Input Port Address Connect, with ImpliedDisconnect Connect the crosspoint cell at the output location specified by RCA[6:0] to the input location specified by RCB[6:0]. All other connections from the same input address or to the same output address are set to no connect (NC). 1010 Output Port Address Input Port Address Connect, without ImpliedDisconnect Connect the crosspoint cell at the output location specified by RCA[6:0] to the input location specified by RCB[6:0]. All other connections to the same output address are set to no connect while all other connections from the same input address remain the same as before. 1011 1100 1101 X X Reserved Reserved Reset All Reset the switch matrix to no connects (NC). Update is forced internally. Sets the Output Buffer to Flow-through mode with Output Enabled.
1000
Output Port Address
Disconnect Input and Output
1110 1111
Reserved Reserved
Note - X = Don't care.
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OCX256 Crosspoint Switch--Advanced Datasheet
Table 4 RCO[4:0] O4
RCO[4:0] Readback Pin Assignment Signal/Function Connection Status: 0 = No connection (NC) -- (default state at reset) 1 = Connected Clock Select: 0 = Global Clock -- (default state at reset) 1 = Next Neighbor Output Mode: 0 = Flow-through (OP) -- (default state at reset) 1 = Registered (RO) Output Enable: Output enabled (ON) - this is the default state at reset Output disabled (OFF) Output controlled by OE (active high) Output controlled by OE# (active low)
Readback Location Crosspoint
O3
Output Buffer
O2
Output Buffer
O1, O0 0,0 0,1 1,0 1,1
Output Buffer
Table 5
Programming an Output Buffer using RapidConfigure Signal/Function Don't care Clock Select: 0 = Global Clock 1 = Next Neighbor Output Mode: 0 = Flow-through (OP) 1 = Registered (RO) Output Enable: Output enabled (ON) - this is the default state at reset Output disabled (OFF) Output controlled by OE (active high) Output controlled by OE# (active low)
RCB[6:0] B6, B5, B4 B3
B2
B1, B0 0,0 0,1 1,0 1,1
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OCX256 Crosspoint Switch--Advanced Datasheet
1.4 JTAG Configuration Controller
The Output port attributes and the Switch Matrix connections can be programmed using the JTAG serial bus. The RapidConfigure Interface can be enabled or disabled using the JTAG serial bus. The JTAG-based serial mode is always available for configuration regardless of whether the RapidConfigure mode is enabled or disabled. However, proper care must be taken when switching between JTAG and RapidConfigure for configuring the devices. Before attempting to change Switch Matrix connections or output port configuration through JTAG, the user must first ensure that the RapidConfigure mode is disabled by using JTAG serial mode to set the RCE bit to zero in the Mode Control Register.
1.4.1
JTAG Interface
The dedicated JTAG TAP interface is designed in compliance with the IEEE-1149.1. The standard interface has five pins: Test Data Out (TDO), Test Mode Select (TMS), Test Data In (TDI), Test Reset (TRST#), and Test Clock (TCK), which allow Boundary Scan Testing as well as device configuration and verification. The Fairchild supplied software will automatically generate the necessary bitstream from a higher-level textual description of the required configuration. Data on the TDI and TMS pins are clocked into the device on the rising edge of the TCK signal, while the valid data appears on the TDO pin after the falling edge of TCK. For more detailed information on JTAG programming, refer to the OCX Family Register Programming Manual.
1.4.2
Output Port Configuration
Output port configuration is accomplished by loading the appropriate bitstream into the programming registers present at each Output port. The JTAG serial bus is used to load configuration data into the Output port programming registers, one Output port at a time.
1.4.3
Switch Matrix Configuration
The contents of the SRAM cells controlling Switch Matrix connection can be modified using the JTAG. This is accomplished by loading the configuration data, one word at a time, into the SRAM cells in the Switch Matrix.
1.4.4
Mode Control Register Configuration
The OCX256 contains a single bit Mode Control Register used to store user flags for RapidConfigure Enable (RCE). These are required for proper functioning of the device. The contents of this register can be changed using the JTAG interface and a special JTAG instruction.
Table 6 RCE 0 1
Mode Control Register Mode RapidConfigure interface disabled (OFF) RapidConfigure interface enabled (ON)
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1.4.5 JTAG Architecture and Shift Registers
Boundary Scan Register (285 x 2 = 570 Bits)
JTAG Data Register - 1 Bit
Device Identification Register - 32 Bits TDI Mode Control Register - 1 Bit
MUX
BUF
TDO
JTAG Address Register - 7 Bits
Bypass Register - 1 Bit
Instruction Register - 16 Bits
TMS TCK
TAP Controller
TRST#
Figure 5
OCX256 JTAG Architecture
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OCX256 Crosspoint Switch--Advanced Datasheet
1.4.6 JTAG State Machine
1
Test Logic Reset 0 1 Run Test/ 1 Idle Select DR Scan 0 Capture DR 0 1 1 Select IR Scan 0 Capture IR 0 1
0
0
Shift DR 1 Exit 1 DR 1 0 Pause DR 1
0
Shift IR 1 Exit 1 IR 1 0 Pause IR 1
0
0
0
Exit 2 DR 1 Update DR 1 0
0
Exit 2 IR 1 Update IR 1 0
Figure 6
OCX256 JTAG State Machine
1.4.7
JTAG Input Format
Table 7 Instruction Bit Number Bit Name 15 I3 14 I2 13 I1 12 I0 11 10 BB BA JTAG Input Format Data 9 B9 8 B8 7 B7 6 A6 5 A5 Address A 4 A4 3 A3 2 A2 1 A1 0 A0
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OCX256 Crosspoint Switch--Advanced Datasheet
1.4.8 JTAG Instructions
Table 8 I [3:0] 0000 0001 0010 BB X X X BA X X X B9 X X X B8 X X X B7 X X X JTAG Instructions A6-A0 X X X Instruction Sample/EXTEST Sample/EXTEST Description Places the device in scan mode. Places the device in scan mode.
Reset the Crosspoint Resets the entire Crosspoint Array to no-connect. All Array other Output Buffer configurations are unchanged by this operation. Set Array for Broadcast mode Use the JTAG Address Register as the Input address to be the broadcast input Connects the selected Input to all Output cells and disconnects all other Inputs. Activating the Global Update JTAG instruction returns the Crosspoint array from the Broadcast mode to the previous programed state. Programs the Output Buffer address specified in the JTAG instruction (A6-A0). The configuration data is also specified in the JTAG instruction bits BA-B7. See Table 9 for bit assignment of the Buffer functionality. Readback the connectivity of the Crosspoint cell with the Input location specified in the JTAG Address Register and the Output location specified JTAG instruction (A0-A6). It also returns the configuration of the Output Buffer addressed in the JTAG instruction (A0-A6). The readback data is shifted out of TDO in the following sequence: 1. Crosspoint Connect (1=connected, 0=no connection) 2. Output Enable--B7 (see Table 9) 3. Output Enable--B8 (see Table 9) 4. Output Data Source--B9 (0=Flow-through, 1=registered) 5. Output Clock Select--BA (0=Global Clock, 1=Next Neighbor) 6. State of Broadcast bit 7. State of the RCE bit NOTE: This instruction does not increment the JTAG Address Register. This instruction also requires two DR cycles
0011
X
X
X
X
X
X
0100
X
Clock Data Select Mode
OE
OE
Output Buffer Address
Program a Buffer
0101
X
X
X
X
X
Output Address/ Configuration Buffer readback
0110 0111
X X
X X
X X
X X
X X
X X
Update the Crosspoint Array Disconnect Input cell
Update the programmed connection from the Loading SRAM to the Active SRAM. Disconnect the Crosspoint connections from the Input address specified in the JTAG Address Register.
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OCX256 Crosspoint Switch--Advanced Datasheet
Table 8 I [3:0] 1000 BB X BA X B9 X B8 X B7 X JTAG Instructions (Continued) A6-A0 Instruction Description Disconnect the Crosspoint cell at the Input location specified at the JTAG Address Register and the Output location specified in the Disconnect JTAG instruction (A6-A0). All other connections from the same input address or to the same output address remain the same. Connects the Crosspoint cell at the Input location specified on the JTAG Address Register and the output location specified in the Connect JTAG instruction (A6-A0). All other connections from the same Input address or the same Output address are set to no-connects. NOTE: This instruction increments the JTAG Address Register (Input address). Connects the Crosspoint cell at the Input address specified in the JTAG Address Register and the Output address specified in the Connect JTAG instruction (A6-A0). All connections to the same output address are set to "no connect" while all other connections from the same input remain the same as before. Sets the 7-bit JTAG Address Register with the 7-bit address (A6-A0) of the JTAG Instruction Register. The 7-bit address of the JTAG Address Register becomes the Input port address for Crosspoint Access. Serialize the device ID and revision history out to TDO. ID for the OCX256 is 0x0000C89F
Output Address Disconnect Input and Output
1001
X
X
X
X
X
Output Address Connect with ImpliedDisconnect
1010
X
X
X
X
X
Output Address Connect--no ImpliedDisconnect
1011
X
X
X
X
X
Input Address
Set the JTAG Address Register
1100 1101
X X
X X
X X
X X
X X
X X
Device ID out
Reset Output Buffer Resets the Crosspoint Array to no-connects. Sets the and Crosspoint Output buffer to Flow-through mode with Output Array Enabled. The device ID is serialized to TDO. Set RCE Bit Sets the RCE bit of the Mode Control Register with the JTAG instruction bit A0. To turn ON the RCE bit, encode bit A0 to 1. To turn OFF the RCE bit, encode bit A0 to 0. Places device in a mode to pass TDI data to TDO with one clock delay. Used for programming and testing devices through serial connected JTAG controls.
1110
X
X
X
X
X
X
1111
X
X
X
X
X
X
Bypass
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OCX256 Crosspoint Switch--Advanced Datasheet
Table 9 BA, B9, B8, B7 BA
Programming an Output using JTAG Signal/Function Clock Select: 0 = Global Clock 1 = Next Neighbor Output Mode: 0 = Flow-through (OP) 1 = Registered (RO) Output Enable: Output enabled (ON) - this is the default state at reset Output disabled (OFF) Output controlled by OE (active high) Output controlled by OE# (active low)
B9
B8, B7 0,0 0,1 1,0 1,1
Table 10
Number of JTAG Cycles and Configuration Time OCX256 Operation JTAG Cycles 7 28 28 3,584 35 56 462,336 456,920
JTAG Reset Sequence (TMS = "11111") Enable or Disable RapidConfigure Change attributes of ONE Output Port Change attributes of ALL Output Ports Reset JTAG Controller + Reset ALL Output Ports + Clear ALL SRAM cells Connect or disconnect two Ports Configure Entire Switch Matrix Completely Configure the Device (All Output Ports and All Switch Matrix Connections)
1.5 ImpliedDisconnect
ImpliedDisconnect is a feature that provides the ability to make fast switch connection changes. When using the instruction "Connect, without ImpliedDisconnect" all other connections to the specified output are set to "no connect". However, the specified input remains connected to any output that it was connected to before. When using the instruction "Connect, with ImpliedDisconnect" all connections from the specified input and to the specified output are set to "no connect". Thus, a connection change, i.e. breaking an existing connection and then making a new one, can be accomplished in one RapidConfigure cycle.
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OCX256 Crosspoint Switch--Advanced Datasheet
1.6 Device Reset Options
The power-on reset, RapidConfigure reset, hardware reset, and JTAG reset functions will program the output buffers to flow-through mode (with Global Clock selected), and Output Enabled (ON). JTAG can be reset via the TRST# pin or by clocking five consecutive one to the TMS pin. The hardware reset pin can be done accomplished through the HW_RST# pin (active low). RC reset can be accomplished by applying the RC instruction 1101 to the RCI[3:0] pins.
Table 11 Programming Interface Reset Method Power-on Reset Hardware Reset HW_RST# (low pulse) 1. Low Pulse on TRST# 2. TMS high for 5 TCLK cycles JTAG Reset 3. Device Reset (instruction 1101) 4. Reset Crosspoint Array (instruction 0010) RapidConfigure Reset 1. Device reset (instruction 1101) 2. Reset Crosspoint Array (instruction 0010) Device Reset Options Output Ports OP OP Unchanged Unchanged OP Unchanged OP Unchanged Switch Matrix NC NC Unchanged Unchanged NC NC NC NC RCE Mode Control 1 (RC Enabled) 1 (RC Enabled) Unchanged Unchanged 1 (RC Enabled) Unchanged 1 (RC Enabled) Unchanged JTAG TAP TLR1 TLR TLR TLR TLR Unchanged Unchanged Unchanged
1. TLR = Test Logic Reset state.
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OCX256 Crosspoint Switch--Advanced Datasheet 2. Pin Description
Table 12 Pin Name INPP[127:0] INN[127:0] OUTP[127:0] OUTN[127:0] CLKP CLKN OE# HW_RST# UPDATE# # of Pins 128 128 128 128 1 1 1 1 1 OCX256 Pin Description Description Non-inverting differential input signals Inverting differential input signals Non-inverting differential input signals Inverting differential input signals Non-inverting differential Global Clock Inverting differential Global Clock Global Output Enable Hardware Reset Global Update
Type Input Input Output Output Input Input Input Input Input
RC Pins
RCA[6:0] RCB[6:0] RCO[4:0] RCI[3:0] RC_CLK# RC_EN# 7 7 5 4 1 1 Input Input Output Input Input Input RapidConfigure Address A RapidConfigure Address B RapidConfigure Readback RapidConfigure Instruction Bits RapidConfigure Clock RapidConfigure Cycle Enable
JTAG Pins
TCK TMS TDI TRST# TDO 1 1 1 1 1 Input Input Input Input Output JTAG Test Clock JTAG Test Mode Select JTAG Test Data In JTAG Test Reset JTAG Test Data Out
Power and Ground Pins
VDD.CORE VDD.PAD VDD.IN VSS
(2) (1, 3)
100 15 16 111
2.5V Power 3.3V Power Ground
Core Voltage LVTTL Control pins Voltage and Differential Input Buffer Voltage Ground
2.5V or 3.3V Power Differential Output Buffer Voltage
NOTES: 1. Dedicated differential input buffers can receive both LVDS and LVPECL voltage levels using 3.3V supply. 2. VDD.PAD is 2.5V for OCX256L or 3.3V for OCX256P. 3. The LVTTL control, JTAG pins, and differential input ports are 3.3V--they are not 5V tolerant. 4. The differential output pins powered from 2.5V are 3.3V tolerant.
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OCX256 Crosspoint Switch--Advanced Datasheet 3. Differential I/O Standards
The OCX256 supports the two most popular differential signaling standards: Low Voltage Differential Signaling (LVDS) and Low Voltage Positive Emitter Coupled Logic (LVPECL). LVDS is typically used in communication systems as high speed, low noise point-to-point links. The OCX256 conforms to the ANSI/TIA/EIA-644 standard covering electrical specifications for output drivers and receiver inputs. LVPECL is commonly used in video switching applications or those designs requiring transmission of highspeed clock signals.
3.1 LVDS
LVDS is a differential signaling standard. It requires that one data bit is carried through two signal lines. As with all differential signaling standards, LVDS has an inherent noise immunity over single-ended standards. The voltage swing between two signal lines is approximately 350mV. The use of a reference voltage or a board termination voltage is not required. LVDS requires the use of two pins per input or output. The OCX256L supports LVDS signalling. Integrated Output Attenuator resistors produce the required LVDS Output swing while providing a 100 ohm output impedance to minimize return reflections.
OCX256L Device
Z0=50 INP RT 110 Z0=50 INN
+ -
VDD.PAD = 2.5V Switch Matrix
Z0=50 OUTP
Z0=50 OUTN
Figure 7
OCX256L LVDS Signal Circuit
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OCX256 Crosspoint Switch--Advanced Datasheet
3.2 LVPECL
LVPECL is another differential signaling standard that specifies two pins per input or output. The voltage swing between these two signal lines is approximately 850 mV. The use of a reference voltage or a board termination voltage is not required. The OCX256P supports LVPECL signalling. Integrated Output Attenuator resistors produce the required LVPECL Output swing while providing a 100 ohm output impedance to minimize return reflections.
OCX256P Device
Z0=50 INP RT 110 Z0=50 INN
+ -
VDD.PAD = 3.3V Switch Matrix
Z0=50 OUTP
Z0=50 OUTN
Figure 8
OCX256P LVPECL Signal Circuit
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OCX256 Crosspoint Switch--Advanced Datasheet 4. Electrical Specifications
4.1 Absolute Maximum Ratings
Table 13 Symbol VDD.CORE VDD.IN VDD.PAD VIN (2) TJ TSTG PMAX ESD
(6)
Absolute Maximum Ratings1 Parameter Limits -0.3 to +3.0 -0.3 to +3.6 -0.3 to +3.6 -0.3 to +3.6 (3) +150 -65 to +150 8.6 2000 Units V V V V C C W V
Supply Voltage (core) Supply Voltage (inputs) Supply Voltage (differential outputs) Input Voltage Junction Temperature Storage Temperature Maximum Power Dissipation Electrostatic Discharge
4.2 Recommended Operating Conditions
Table 14 Symbol VDD.CORE VDD.PAD VDD.IN TA
(4)
Recommended Operating Conditions Parameter Limits +2.375 to +2.625 3.3V 10% or 2.5V 5% +3.0 to +3.6 0 to +70 -40 to +85 Units V V V C
Supply Voltage (core) Supply Voltage (differential output buffers) Supply Voltage (inputs) Operating Temperature: Commercial Operating Temperature: Industrial
4.3 Pin Capacitance
Table 15 Symbol CPIN
1. 2. 3. 4. 5. 6.
Pin Capacitance5 Parameter Max 10 Units pF
Signal Pin Capacitance
Exposure to absolute maximum rated conditions for extended periods may affect device reliability. A maximum undershoot of 2V for a maximum duration of 20 ns is acceptable. Overshoot to 3.6V is acceptable. All inputs are 3.3V tolerant with the VDD pin at 2.5V or 3.3V. Note that min and max values for VDD for differential outputs are I/O Standard dependent. Capacitance measured at 25C. Sample tested only. Measured using Human Body Model.
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OCX256 Crosspoint Switch--Advanced Datasheet
4.4 DC Electrical Specifications
(TA = -40C to 85C, VDD.IN = 3.3V 10%, VDD.CORE = 2.5V 5%) Table 16 Symbol VIH VIL VOH VOL ILIH, ILIL (1) ILOZ Parameter High-level Input Low-level Input High-level Output Low-level Output Input Pin Leakage Current
(2)
LVTTL DC Electrical Specifications Conditions Ports are 3.3V tolerant Ports are 3.3V tolerant VDD.PAD = Min IOH = -4mA VDD.PAD = Min IOL = 8mA VDD.IN= Max 0.0 < In < VDD.PAD VDD.PAD = Max 0.0 < In < VDD.PAD Min 2.0 -0.3 2.4 Max 3.6 0.8 VDD.PAD+ 0.3 0.4 +5 -50 +5 -5 Units V V V V
Tristate Leakage Output OFF State (2)
Power
PDDQ (3) Quiescent Power All VDD = Max 0.7 W
Table 17
OCX256L (LVDS) DC Electrical Specifications (VDD.PAD = 2.5V) DC Parameter Min 0.90 250 1.125 100 0.25 88 350 1.25 350 1.25 2.25 132 450 1.375 Typ Max 1.6 Units V V mV V mV V
Output High Voltage for OUTP and OUTN Output Low Voltage for OUTP and OUTN Differential Output Voltage Differential Input Voltage Input Common-Mode Voltage ZIN -- Termination Impedance
1. 2. 3. 4. All LVTTL input pins have pull-up resistors.
(4)
Output Common-Mode Voltage
Input leakage only valid when both positive and negative inputs/outputs area equal (i.e. both high or both low) See section 6 for dynamic power consumption calculation. Maximum capacitive load is 12 pF.
Table 18 Symbol VIN_DIFF VIN_COM
OCX256P (LVPECL) DC Electrical Specifications (VDD.PAD = 3.3V) DC Parameters Input Differential Voltage Input Common Mode Voltage Output Differential Voltage Output Common Mode Voltage Termination Impedance Min 100 0.25 350 VDD.PAD 2 80 2.25 650 VDD.PAD 2 120 Max Units mV V mV V
VOUT_DIFF VOUT_COM ZIN
The VOH levels are 200mV below LVPECL levels and are compatible with devices tolerant of lower common-mode ranges. The above table summarizes the DC output specifications of LVPECL.
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OCX256 Crosspoint Switch--Advanced Datasheet
4.5 AC Electrical Specifications
(VDD.IN = 3.3V 10%, VDD.CORE = 2.5V 5%) Table 19 AC Electrical Specifications 0C to 70C Symbol RDATA FRO tW_RO tS_RO tH_RO tCO_RO tPHL, tPLH tW+ tWtDCD+, tDCDtJITTER tSK tPHZ_OT, tPLZ_OT tPZH_OT, tPZL_OT tRC tW+_RC tW-_RC tS_RC tH_RC tP_UD fJTAG tW_JTAG tS_JTAG tH_JTAG tP_JTAG NRZ Data Rate
(1) (1) (1)
-40C to +85C Min Max 667 333 2 4 0 Units Mb/s MHz ns ns ns 2.5 6.5 1.5 1.5 ns ns ns ns 0.6 0.5 0.6 3 3 12 5 4 4 ns ns ns ns ns ns ns ns ns 10 20 20 4 0 30 ns MHz ns ns ns 20 ns
Parameter Registered Output Clock Frequency
Min
Max 667 333
Registered Clock Pulse Width, High or Low Registered Output Setup Time to Clock Registered Output Clock to Hold Data Registered Output Clock to Data Out Valid
2 4 0 2.5 5.5 1.5 1.5 0.5 0.5
One Way Signal Propagation Delay, Fanout = 1 Input Flow-through Positive Pulse Width Input Flow-through Negative Pulse Width Duty Cycle Distortion Output Jitter Skew between Output Ports Output Enable to Valid Data Output Enable to High Z State RapidConfigure Clock Period RapidConfigure Clock Pulse Width RapidConfigure Address Setup to RC_CLK# RapidConfigure Address and Enable Hold Time to RC_CLK# Update of Crosspoint to Data Out JTAG Clock Frequency (TCK) JTAG Clock Pulse Width (TCK) @ 20MHz cycle JTAG Setup Time JTAG Hold Time JTAG Clock to Output Data Valid (TDO) 20 4 0 12 5 3 3
(1)
0.5 3 3
10 20 30
20
NOTES:
1. These parameters are guaranteed but not tested in production.
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OCX256 Crosspoint Switch--Advanced Datasheet
4.6 Timing Diagrams
Note - For the purpose of clarity, the timing diagrams within this datasheet are conceptual representations only and do not show actual circuit implementation.
tW_RO CLK tS_RO tH_RO IN
InPort CLK
tW_RO
RO
Switch Matrix
D Q OutPort
InPort OutPort
Dn Dn-1 tCO_RO
Dn+1 Dn Dn+1
Figure 9
Registered Output Mode Timing
InPort 1 InPort 2
tW+ tPLH tPHL
IN
InPort 1
OP
OutPort 1
OutPort 1 tSK
OutPort 2
Switch Matrix
InPort 2
tSK
OutPort 2
Figure 10 Flow-Through Mode Timing
OE#
InPort IN
InPort OE#
tPZH_OT tPZL_OT tPLZ_OT
tPHZ_OT
Switch Matrix
OP
OutPort
OutPort
Figure 11 Output Enable Timing
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OCX256 Crosspoint Switch--Advanced Datasheet
IN InPort
Switch Matrix
OP OutPort
InPort
tIN+
tIN-
OutPort
tOUT+ tDCD+ = tIN+ - tOUT+ tDCD- = tIN- - tOUT-
tOUT-
Figure 12 Duty Cycle Distortion
tRC tW+_RC RC_CLK# tS_RC RCA/RCB Address, Instruction tS_RC tH_RC RC_EN# tH_RC tW-_RC
tRC
Figure 13 RapidConfigure Write Cycle
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OCX256 Crosspoint Switch--Advanced Datasheet
tRC tW+_RC RC_CLK# tW-_RC
tRC
tS_RC RCA/RCB Address, Instruction
tH_RC
tS_RC tH_RC RC_EN#
Data Valid
RCO
High Impedance
Figure 14 RapidConfigure Read Cycle
tW_JTAG TCK
tW_JTAG
tS_JTAG tH_JTAG TDI, TMS tP_JTAG TDO
Figure 15 JTAG Timing
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OCX256 Crosspoint Switch--Advanced Datasheet
Figure 16 Typical Performance at 667 Mb/s with PRBS Data
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OCX256 Crosspoint Switch--Advanced Datasheet 5. Package and Pinout
5.1 Package Pinout
1
Vss
2
3
Vss
4
5
OUT01P
6
7
Vss
8
9
OUT09N
10
11
Vss
12
13
OUT17P
14
15
Vss
16
17
OUT27N
18
19
Vss
20
21
Vss
22
23
OUT37P
24
25
Vss
26
27
OUT47N
28
29
Vss
30
31
VDD.PAD
32
33
Vss
34
35
Vss
36
37
Vss
38
39
Vss
A
Vss Vss Vss Vss Vss Vss Vss Vss Vss NC IN127P TRST# TDI IN124N IN127N IN126P Vss IN124P IN123N IN121N IN122N IN122P Vss IN120N IN120P IN117P IN118P IN117N IN114P IN115P IN114N IN111P IN112P IN111N Vss IN110P IN109N IN107N IN108N IN108P Vss IN105N IN105P IN103P IN104P IN103N Vss IN101P IN100N IN99N IN101N VDD.IN VDD.IN IN96N IN97N IN97P IN94N IN96P IN95P Vss IN92P IN94P IN91N IN90N IN91P IN89N IN88N IN89P IN86N IN85N IN86P Vss IN84P IN84N IN82P IN81P IN81N IN79P IN80N VDD.IN IN78N IN77N IN78P IN74N IN76P IN76N IN74P IN73P IN73N IN70P IN71N IN72P IN69N IN68N IN69P Vss IN67P IN67N IN65N IN64P IN65P Vss RC_EN# RC_CLK# Vss Vss RCI3 Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss RCI2 OUT126P OUT124N Vss RCB4 OUT127P Vss OUT121N Vss RCB6 RCB5 Vss RCI0 IN66N VDD.CORE IN68P IN66P IN64N OUT127N VDD.PAD OUT116P OUT112N OUT108P OUT103P OUT99N OUT93P OUT88P OUT84N VDD.PAD OUT75P IN71P VDD.CORE VDD.CORE IN72N IN70N Vss IN75N VDD.CORE VDD.CORE IN77P IN75P Vss IN80P VDD.CORE VDD.CORE VDD.IN IN79N Vss IN83N VDD.CORE VDD.CORE IN85P IN83P IN82N IN88P VDD.CORE VDD.CORE IN90P IN87N IN87P IN93N VDD.CORE VDD.CORE IN95N IN93P IN92N IN98P VDD.CORE VDD.CORE IN100P IN98N IN99P VDD.CORE VDD.CORE IN104N IN102P IN102N IN106P VDD.CORE VDD.CORE IN109P IN106N IN107P IN110N VDD.CORE VDD.CORE IN112N VDD.IN VDD.IN IN115N IN113P IN113N IN118N IN116P IN116N VDD.IN IN119P IN119N IN123P VDD.IN IN121P IN125P VDD.CORE VDD.CORE TMS IN125N IN126N Vss TCK VDD.CORE Vss Vss Vss Vss RCO4 OUT01N HW_RST# OUT00N VDD.CORE Vss VDD.PAD UPDATE# TDO OUT00P OUT02N OUT04P OUT07N VDD.CORE OUT06P OUT02P OUT03P OUT05N OUT07P OUT09P OUT12N OUT03N OUT04N OUT05P OUT08N OUT10N OUT12P OUT13N OUT15P OUT06N OUT08P OUT10P VDD.PAD OUT13P OUT16N OUT18N OUT20P OUT11N VDD.PAD OUT14N OUT16P OUT18P OUT21N OUT22P OUT25N OUT14P OUT17N OUT19N OUT21P OUT23N OUT25P OUT27P OUT30N OUT19P OUT22N OUT23P OUT26N OUT28N OUT30P OUT32P OUT34P OUT24N OUT26P OUT28P OUT31N OUT33N OUT34N OUT37N OUT39P OUT29N OUT31P OUT32N VDD.PAD OUT36P OUT39N OUT42N OUT44N OUT33P VDD.PAD OUT36N OUT38P OUT41P OUT43P OUT46P OUT49N OUT35P OUT38N OUT41N OUT43N OUT46N OUT48P OUT51P OUT53P OUT40P OUT42P OUT45P OUT48N OUT51N OUT53N VDD.PAD OUT45N OUT47P OUT50P OUT52P OUT55P OUT50N OUT52N OUT55N OUT54P
OUT58P OUT56N OUT59N OUT56P OUT59P OUT57N OUT60N OUT57P OUT62P OUT62N OUT61N OUT60P
OUT61P OUT63P OUT63N RCO3 RCO2 Vss OE# Vss NC CLKN VDD.CORE IN01N
Vss Vss RCO1 Vss Vss Vss Vss CLKP Vss RCA1 RCA0 IN02N VDD.IN VDD.CORE IN05N IN04N IN07N IN08N IN08P IN10P IN11P IN10N IN13P IN14P IN13N VDD.CORE IN15P VDD.IN IN17P IN18P IN17N VDD.CORE IN19N IN19P IN21N IN22N IN22P VDD.CORE IN24N IN24P IN26N IN27N IN27P VDD.CORE IN29P IN28N IN31P IN32P IN31N VDD.CORE IN33N VDD.IN IN35N IN34N IN35P VDD.CORE IN37N IN38P IN40P IN39P IN39N VDD.CORE IN42P IN42N IN44N IN43N IN44P VDD.CORE IN46N IN47P IN49P IN48P IN48N VDD.CORE IN51P IN51N IN53N IN52N IN53P VDD.CORE IN55N IN56P IN57N VDD.IN IN57P VDD.CORE IN59N IN60P IN63P IN61N IN62N VDD.CORE RCA6 Vss Vss Vss Vss Vss RCB1 Vss RCB3 Vss OUT64P Vss Vss Vss Vss RCB0 RCA3
Vss Vss
A B
B C
Vss Vss Vss Vss IN00P IN03P IN01P IN03N
C D E F
D E
VDD.CORE VDD.CORE VDD.CORE VDD.CORE VDD.CORE VDD.CORE VDD.CORE VDD.CORE VDD.CORE VDD.CORE VDD.CORE VDD.CORE OUT11P OUT35N OUT44P OUT49P OUT54N OUT58N RCO0 OUT15N OUT40N OUT20N OUT24P OUT29P VDD.CORE VDD.CORE VDD.CORE VDD.CORE VDD.CORE VDD.CORE VDD.CORE VDD.CORE VDD.CORE VDD.CORE VDD.CORE VDD.CORE
F
IN00N IN05P IN04P IN06N IN06P Vss IN09P IN12P
G H J K
IN09N IN11N VDD.IN IN14N IN16P IN15N Vss IN18N IN20N
0-63 Outputs
IN02P
G H J K L M N P
VDD.CORE
IN07P
L
IN12N
M
VDD.CORE
N P R T U V W Y AA AB AC
OCX256 in 792 TBGA
64-127 Inputs Top View 0-63 Inputs
IN16N
VDD.CORE
IN20P IN23N
R
IN21P IN23P IN25N IN25P Vss IN28P IN30P
T U V
VDD.CORE
IN26P
VDD.CORE
IN29N Vss
W
IN30N IN32N VDD.IN IN33P Vss IN34P IN36N
Y AA AB
VDD.CORE
IN36P
VDD.CORE
IN37P Vss
AC
IN40N IN38N IN41P IN41N Vss IN43P IN45N IN46P Vss
AD
VDD.CORE
AD AE AF AG
AE
IN45P
AF AG
IN49N
VDD.CORE
IN47N IN50P IN50N Vss IN52P IN54N IN55P IN56N
AH
VDD.CORE
AH AJ AK AL
AJ
IN54P
AK AL M AN
IN63N OUT70N OUT65N IN60N IN61P
64-127 Outputs
VDD.CORE
IN58P
VDD.IN IN58N
AM
VDD.CORE IN59P Vss
AN AP
AP
Vss
AR
VDD.IN Vss
OUT123P VDD.CORE VDD.CORE VDD.CORE VDD.CORE VDD.CORE VDD.CORE VDD.CORE VDD.CORE VDD.CORE VDD.CORE OUT72P VDD.CORE VDD.CORE VDD.CORE OUT120P OUT116N OUT111P OUT103N VDD.PAD VDD.PAD OUT89N OUT84P OUT126N OUT108N OUT94N OUT76N OUT70P OUT65P RCI1 OUT123N OUT73N VDD.CORE VDD.CORE VDD.CORE VDD.CORE VDD.CORE VDD.CORE VDD.CORE VDD.CORE VDD.CORE VDD.CORE VDD.CORE OUT120N OUT111N OUT102P OUT125P OUT115P OUT94P OUT89P VDD.PAD OUT85N OUT80N OUT107P OUT76P OUT71N OUT67N OUT118P OUT114N OUT101N OUT122P OUT105P OUT91P OUT86P VDD.PAD OUT97N OUT78N OUT82N OUT73P OUT119P OUT110P OUT102N OUT125N OUT95N OUT90N OUT115N OUT107N OUT98P OUT85P OUT80P OUT77N OUT71P OUT118N OUT122N OUT124P OUT119N OUT121P Vss OUT117N OUT117P NC OUT66P RCB2
RCA2 IN62P
AR
RCA4 Vss RCA5 Vss Vss Vss
AT AU
VDD.PAD
AT AU AV
Vss
OUT113P OUT105N OUT100P OUT92N OUT87N OUT64N OUT82P OUT96P OUT78P OUT74N OUT68P VDD.PAD OUT110N OUT106P OUT101P OUT98N OUT95P OUT90P OUT86N OUT81N OUT77P OUT72N OUT67P OUT109P Vss OUT109N OUT106N OUT104N OUT104P Vss OUT99P OUT100N Vss OUT96N OUT97P Vss OUT93N OUT92P OUT91N OUT88N OUT87P Vss OUT83P OUT83N OUT81P OUT79P OUT79N Vss OUT75N OUT74P Vss OUT69P OUT69N Vss OUT68N OUT66N
AV
OUT113N OUT114P OUT112P Vss Vss
W
Vss
AW 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
Figure 17 OCX256 Package Pinout
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OCX256 Crosspoint Switch--Advanced Datasheet
5.2 Pinout by Ball Sequence
Table 20 Ball # Ball Name
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 VSS VSS VSS VSS OUT01P OUT03N VSS OUT06N OUT09N OUT11N VSS OUT14P OUT17P OUT19P VSS OUT24N OUT27N OUT29N VSS OUT33P VSS OUT35P OUT37P OUT40P VSS OUT45N OUT47N OUT50N VSS OUT54P VDD.PAD OUT58P VSS OUT61P VSS VSS VSS VSS VSS
OCX256 Pinout By Ball Sequence Ball # Ball Name
D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 D32 D33 D34 D35 D36 D37 D38 D39 VSS NC VSS VSS VSS RCO4 OUT02N OUT04P OUT07P OUT09P OUT12P OUT13N OUT16N OUT18N OUT21N OUT22P OUT25P OUT27P OUT30P OUT32P OUT34N OUT37N OUT39N OUT42N OUT43P OUT46P OUT48P OUT51P OUT53N VDD.PAD OUT57N OUT60N OUT62N OE# VSS VSS VSS IN00P VSS
Ball # Ball Name
B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 VSS VSS VSS UPDATE# VDD.PAD OUT02P OUT04N OUT05P OUT08P OUT10P VDD.PAD OUT14N OUT17N OUT19N OUT22N OUT23P OUT26P OUT28P OUT31P OUT32N VDD.PAD OUT36N OUT38N OUT41N OUT42P OUT45P OUT47P OUT50P OUT52N OUT55N OUT56N OUT59N OUT60P OUT63N OUT63P RCO1 VSS VSS VSS
Ball # Ball Name
C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 C33 C34 C35 C36 C37 C38 C39 VSS VSS VSS VSS TDO OUT00P OUT03P OUT05N OUT08N OUT10N VDD.PAD OUT13P OUT16P OUT18P OUT21P OUT23N OUT26N OUT28N OUT31N OUT33N VDD.PAD OUT36P OUT38P OUT41P OUT43N OUT46N OUT48N OUT51N OUT52P OUT55P OUT56P OUT59P OUT61N RCO2 RCO3 VSS VSS VSS VSS
Ball # Ball Name
E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 E23 E24 E25 E26 E27 E28 E29 E30 E31 E32 E33 E34 E35 E36 E37 E38 E39 IN127P TDI TRST# VSS VSS HW_RST# OUT01N VDD.CORE OUT07N VDD.CORE OUT12N VDD.CORE OUT15P VDD.CORE OUT20P VDD.CORE OUT25N VDD.CORE OUT30N VDD.CORE OUT34P VDD.CORE OUT39P VDD.CORE OUT44N VDD.CORE OUT49N VDD.CORE OUT53P VDD.CORE OUT57P VDD.CORE OUT62P NC VSS VSS CLKP IN01P IN03P
Ball # Ball Name
F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 F32 F33 F34 F35 F36 F37 F38 F39 IN124N IN126P IN127N TMS TCK VDD.CORE OUT00N VDD.CORE OUT06N VDD.CORE OUT11P VDD.CORE OUT15N VDD.CORE OUT20N VDD.CORE OUT24P VDD.CORE OUT29P VDD.CORE OUT35N VDD.CORE OUT40N VDD.CORE OUT44P VDD.CORE OUT49P VDD.CORE OUT54N VDD.CORE OUT58N VDD.CORE RCO0 VDD.CORE CLKN RCA0 RCA1 IN00N IN03N
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OCX256 Crosspoint Switch--Advanced Datasheet
Table 20 Ball # Ball Name
G1 G2 G3 G4 G5 G6 G34 G35 G36 G37 G38 G39 N1 N2 N3 N4 N5 N6 N34 N35 N36 N37 N38 N39 W1 W2 W3 W4 W5 W6 W34 W35 W36 W37 W38 W39 VSS IN123N IN124P IN125P IN125N IN126N IN02P IN01N VDD.IN IN02N IN04P IN05P VSS IN109N IN110P IN110N VDD.IN VDD.IN IN16N IN17P IN17N IN18P IN18N VSS IN96N IN97P IN97N IN98P IN98N IN99P IN30N IN31P IN31N IN32P IN32N VSS
OCX256 Pinout By Ball Sequence (Continued) Ball # Ball Name
K1 K2 K3 K4 K5 K6 K34 K35 K36 K37 K38 K39 T1 T2 T3 T4 T5 T6 T34 T35 T36 T37 T38 T39 AB1 AB2 AB3 AB4 AB5 AB6 AB34 AB35 AB36 AB37 AB38 AB39 IN117P IN117N IN118P IN118N IN119P IN119N IN09N IN10P IN10N IN11P IN11N IN12P IN103P IN103N IN104P IN104N VDD.CORE VDD.CORE VDD.CORE VDD.CORE IN24P IN24N IN25P IN25N IN91N IN91P IN90N IN90P VDD.CORE VDD.CORE VDD.CORE VDD.CORE IN38P IN37N IN37P IN36N
Ball # Ball Name
H1 H2 H3 H4 H5 H6 H34 H35 H36 H37 H38 H39 P1 P2 P3 P4 P5 P6 P34 P35 P36 P37 P38 P39 Y1 Y2 Y3 Y4 Y5 Y6 Y34 Y35 Y36 Y37 Y38 Y39 IN121N IN122P IN122N IN123P VDD.CORE VDD.CORE VDD.CORE VDD.CORE IN04N IN05N IN06P IN06N IN107N IN108P IN108N IN109P VDD.CORE VDD.CORE VDD.CORE VDD.CORE IN19P IN19N IN20P IN20N IN94N IN95P IN96P IN95N VDD.CORE VDD.CORE VDD.CORE VDD.CORE VDD.IN IN33N IN33P VDD.IN
Ball # Ball Name
J1 J2 J3 J4 J5 J6 J34 J35 J36 J37 J38 J39 R1 R2 R3 R4 R5 R6 R34 R35 R36 R37 R38 R39 AA1 AA2 AA3 AA4 AA5 AA6 AA34 AA35 AA36 AA37 AA38 AA39 VSS IN120P IN120N VDD.IN VDD.IN IN121P IN07P IN07N IN08P IN08N IN09P VSS VSS IN105P IN105N IN106P IN106N IN107P IN21P IN21N IN22P IN22N IN23P IN23N VSS IN94P IN92P IN93N IN93P IN92N IN36P IN35N IN35P IN34N IN34P VSS
Ball # Ball Name
L1 L2 L3 L4 L5 L6 L34 L35 L36 L37 L38 L39 U1 U2 U3 U4 U5 U6 U34 U35 U36 U37 U38 U39 AC1 AC2 AC3 AC4 AC5 AC6 AC34 AC35 AC36 AC37 AC38 AC39 IN114P IN114N IN115P IN115N IN116P IN116N IN12N IN13P IN13N IN14P IN14N VDD.IN VSS IN100N IN101P IN101N IN102P IN102N IN26P IN26N IN27P IN27N IN28P VSS IN89N IN89P IN88N IN88P IN87N IN87P IN40N IN40P IN39N IN39P IN38N VSS
Ball # Ball Name
M1 M2 M3 M4 M5 M6 M34 M35 M36 M37 M38 M39 V1 V2 V3 V4 V5 V6 V34 V35 V36 V37 V38 V39 AD1 AD2 AD3 AD4 AD5 AD6 AD34 AD35 AD36 AD37 AD38 AD39 IN111P IN111N IN112P IN112N IN113P IN113N VDD.CORE VDD.CORE VDD.IN IN15P IN15N IN16P IN99N VDD.IN VDD.IN IN100P VDD.CORE VDD.CORE VDD.CORE VDD.CORE IN28N IN29P IN29N IN30P IN86N IN86P IN85N IN85P VDD.CORE VDD.CORE VDD.CORE VDD.CORE IN42N IN42P IN41N IN41P
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33
OCX256 Crosspoint Switch--Advanced Datasheet
Table 20 Ball # Ball Name
AE1 AE2 AE3 AE4 AE5 AE6 AE34 AE35 AE36 AE37 AE38 AE39 AL1 AL2 AL3 AL4 AL5 AL6 AL34 AL35 AL36 AL37 AL38 AL39 VSS IN84N IN84P IN83N IN83P IN82N IN45P IN44N IN44P IN43N IN43P VSS IN70P IN72P IN71N IN71P IN70N VSS IN58P IN57N IN57P VDD.IN VDD.IN IN56N
OCX256 Pinout By Ball Sequence (Continued) Ball # Ball Name
AH1 AH2 AH3 AH4 AH5 AH6 AH34 AH35 AH36 AH37 AH38 AH39 IN78N IN78P IN77N IN77P VDD.CORE VDD.CORE VDD.CORE VDD.CORE IN51N IN51P IN50N IN50P
Ball # Ball Name
AF1 AF2 AF3 AF4 AF5 AF6 AF34 AF35 AF36 AF37 AF38 AF39 AM1 AM2 AM3 AM4 AM5 AM6 AM34 AM35 AM36 AM37 AM38 AM39 IN82P IN81N IN81P VDD.IN VDD.CORE VDD.CORE VDD.CORE VDD.CORE IN47P IN46N IN46P IN45N IN69N IN69P IN68N IN68P VDD.CORE VDD.CORE VDD.CORE VDD.CORE IN60P IN59N IN59P IN58N
Ball # Ball Name
AG1 AG2 AG3 AG4 AG5 AG6 AG34 AG35 AG36 AG37 AG38 AG39 AN1 AN2 AN3 AN4 AN5 AN6 AN34 AN35 AN36 AN37 AN38 AN39 IN79P VDD.IN IN80N IN80P IN79N VSS IN49N IN49P IN48N IN48P IN47N VSS VSS IN67N IN67P IN66N IN66P IN64N IN63N IN63P IN62N IN61N IN60N VSS
Ball # Ball Name
AJ1 AJ2 AJ3 AJ4 AJ5 AJ6 AJ34 AJ35 AJ36 AJ37 AJ38 AJ39 IN74N IN76N IN76P IN75N IN75P VSS IN54P IN53N IN53P IN52N IN52P VSS
Ball # Ball Name
AK1 AK2 AK3 AK4 AK5 AK6 AK34 AK35 AK36 AK37 AK38 AK39 IN74P IN73N IN73P IN72N VDD.CORE VDD.CORE VDD.CORE VDD.CORE IN56P IN55N IN55P IN54N
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OCX256 Crosspoint Switch--Advanced Datasheet
Table 20 Ball # Ball Name
AP1 AP2 AP3 AP4 AP5 AP6 AP7 AP8 AP9 AP10 AP11 AP12 AP13 AP14 AP15 AP16 AP17 AP18 AP19 AP20 AP21 AP22 AP23 AP24 AP25 AP26 AP27 AP28 AP29 AP30 AP31 AP32 AP33 AP34 AP35 AP36 AP37 AP38 AP39 IN65N IN65P IN64P RC_EN# VDD.CORE VDD.CORE OUT127N OUT123P VDD.PAD VDD.CORE OUT116P VDD.CORE OUT112N VDD.CORE OUT108P VDD.CORE OUT103P VDD.CORE OUT99N VDD.CORE OUT93P VDD.CORE OUT88P VDD.CORE OUT84N VDD.CORE VDD.PAD VDD.CORE OUT75P OUT72P OUT70N VDD.CORE OUT65N VDD.CORE VDD.CORE RCA6 RCA3 RCA2 IN61P
OCX256 Pinout By Ball Sequence (Continued) Ball # Ball Name
AU1 AU2 AU3 AU4 AU5 AU6 AU7 AU8 AU9 AU10 AU11 AU12 AU13 AU14 AU15 AU16 AU17 AU18 AU19 AU20 AU21 AU22 AU23 AU24 AU25 AU26 AU27 AU28 AU29 AU30 AU31 AU32 AU33 AU34 AU35 AU36 AU37 AU38 AU39 VSS VSS VSS VSS RCB6 RCB5 OUT125N OUT122N OUT119P OUT118N OUT115N OUT113P OUT110P VDD.PAD OUT107N OUT105N OUT102N OUT100P OUT98P OUT96P OUT95N OUT92N OUT90N OUT87N OUT85P OUT82P OUT80P OUT78P OUT77N OUT74N OUT71P OUT68P OUT66P OUT64N RCB1 VSS VSS VSS VSS
Ball # Ball Name
AR1 AR2 AR3 AR4 AR5 AR6 AR7 AR8 AR9 AR10 AR11 AR12 AR13 AR14 AR15 AR16 AR17 AR18 AR19 AR20 AR21 AR22 AR23 AR24 AR25 AR26 AR27 AR28 AR29 AR30 AR31 AR32 AR33 AR34 AR35 AR36 AR37 AR38 AR39 VSS VDD.IN RC_CLK# VSS VSS RCI1 OUT126N OUT123N OUT120P VDD.CORE OUT116N VDD.CORE OUT111P VDD.CORE OUT108N VDD.CORE OUT103N VDD.CORE VDD.PAD VDD.CORE OUT94N VDD.CORE OUT89N VDD.CORE OUT84P VDD.CORE VDD.PAD VDD.CORE OUT76N OUT73N OUT70P VDD.CORE OUT65P RCB2 VSS VSS RCB0 RCA4 IN62P
Ball # Ball Name
AT1 AT2 AT3 AT4 AT5 AT6 AT7 AT8 AT9 AT10 AT11 AT12 AT13 AT14 AT15 AT16 AT17 AT18 AT19 AT20 AT21 AT22 AT23 AT24 AT25 AT26 AT27 AT28 AT29 AT30 AT31 AT32 AT33 AT34 AT35 AT36 AT37 AT38 AT39 VSS RCI3 VSS VSS VSS RCI0 OUT125P OUT122P OUT120N OUT118P OUT115P OUT114N OUT111N VDD.PAD OUT107P OUT105P OUT102P OUT101N VDD.PAD OUT97N OUT94P OUT91P OUT89P OUT86P OUT85N OUT82N OUT80N OUT78N OUT76P OUT73P OUT71N NC OUT67N VDD.PAD VSS VSS VSS RCA5 VSS
Ball # Ball Name
AV1 AV2 AV3 AV4 AV5 AV6 AV7 AV8 AV9 AV10 AV11 AV12 AV13 AV14 AV15 AV16 AV17 AV18 AV19 AV20 AV21 AV22 AV23 AV24 AV25 AV26 AV27 AV28 AV29 AV30 AV31 AV32 AV33 AV34 AV35 AV36 AV37 AV38 AV39 VSS VSS VSS RCI2 RCB4 OUT127P OUT124P OUT121P OUT119N OUT117P VSS OUT113N OUT110N OUT109P OUT106P OUT104P OUT101P OUT100N OUT98N OUT97P OUT95P OUT92P OUT90P OUT87P OUT86N OUT83N OUT81N OUT79N OUT77P OUT74P OUT72N OUT69N OUT67P OUT66N RCB3 VSS VSS VSS VSS
Ball # Ball Name
AW1 AW2 AW3 AW4 AW5 AW6 AW7 AW8 AW9 AW10 AW11 AW12 AW13 AW14 AW15 AW16 AW17 AW18 AW19 AW20 AW21 AW22 AW23 AW24 AW25 AW26 AW27 AW28 AW29 AW30 AW31 AW32 AW33 AW34 AW35 AW36 AW37 AW38 AW39 VSS VSS VSS VSS OUT126P OUT124N VSS OUT121N VSS OUT117N OUT114P OUT112P VSS OUT109N OUT106N OUT104N VSS OUT99P VSS OUT96N VSS OUT93N OUT91N OUT88N VSS OUT83P OUT81P OUT79P VSS OUT75N VSS OUT69P VSS OUT68N OUT64P VSS VSS VSS VSS
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OCX256 Crosspoint Switch--Advanced Datasheet
5.3 Pinout by Ball Name
Table 21 Ball Name
CLKN CLKP HW_RST# IN00N IN00P IN01N IN01P IN02N IN02P IN03N IN03P IN04N IN04P IN05N IN05P IN06N IN06P IN07N IN07P IN08N IN08P IN09N IN09P IN10N IN10P IN11N IN11P IN12N IN12P IN13N IN13P IN14N IN14P IN15N IN15P IN16N IN16P IN17N IN17P IN18N IN18P IN19N IN19P IN20N IN20P IN21N
OCX256 Pinout By Ball Name Ball # Ball Name
AE36 AF39 AE34 AF37 AF38 AG38 AF36 AG36 AG37 AG34 AG35 AH38 AH39 AH36 AH37 AJ37 AJ38 AJ35 AJ36 AK39 AJ34 AK37 AK38 AL39 AK36 AL35 AL36 AM39 AL34 AM37 AM38 AN38 AM36 AN37 AP39 AN36 AR39 AN34 AN35 AN6 AP3 AP1 AP2 AN4 AN5 AN2 IN67P IN68N IN68P IN69N IN69P IN70N IN70P IN71N IN71P IN72N IN72P IN73N IN73P IN74N IN74P IN75N IN75P IN76N IN76P IN77N IN77P IN78N IN78P IN79N IN79P IN80N IN80P IN81N IN81P IN82N IN82P IN83N IN83P IN84N IN84P IN85N IN85P IN86N IN86P IN87N IN87P IN88N IN88P IN89N IN89P IN90N
Ball # Ball Name
F35 E37 E6 F38 D38 G35 E38 G37 G34 F39 E39 H36 G38 H37 G39 H39 H38 J35 J34 J37 J36 K34 J38 K36 K35 K38 K37 L34 K39 L36 L35 L38 L37 M38 M37 N34 M39 N36 N35 N38 N37 P37 P36 P39 P38 R35 IN21P IN22N IN22P IN23N IN23P IN24N IN24P IN25N IN25P IN26N IN26P IN27N IN27P IN28N IN28P IN29N IN29P IN30N IN30P IN31N IN31P IN32N IN32P IN33N IN33P IN34N IN34P IN35N IN35P IN36N IN36P IN37N IN37P IN38N IN38P IN39N IN39P IN40N IN40P IN41N IN41P IN42N IN42P IN43N IN43P IN44N
Ball # Ball Name
R34 R37 R36 R39 R38 T37 T36 T39 T38 U35 U34 U37 U36 V36 U38 V38 V37 W34 V39 W36 W35 W38 W37 Y37 Y38 AA37 AA38 AA35 AA36 AB39 AA34 AB37 AB38 AC38 AB36 AC36 AC37 AC34 AC35 AD38 AD39 AD36 AD37 AE37 AE38 AE35 IN44P IN45N IN45P IN46N IN46P IN47N IN47P IN48N IN48P IN49N IN49P IN50N IN50P IN51N IN51P IN52N IN52P IN53N IN53P IN54N IN54P IN55N IN55P IN56N IN56P IN57N IN57P IN58N IN58P IN59N IN59P IN60N IN60P IN61N IN61P IN62N IN62P IN63N IN63P IN64N IN64P IN65N IN65P IN66N IN66P IN67N
Ball # Ball Name
AN3 AM3 AM4 AM1 AM2 AL5 AL1 AL3 AL4 AK4 AL2 AK2 AK3 AJ1 AK1 AJ4 AJ5 AJ2 AJ3 AH3 AH4 AH1 AH2 AG5 AG1 AG3 AG4 AF2 AF3 AE6 AF1 AE4 AE5 AE2 AE3 AD3 AD4 AD1 AD2 AC5 AC6 AC3 AC4 AC1 AC2 AB3 IN90P IN91N IN91P IN92N IN92P IN93N IN93P IN94N IN94P IN95N IN95P IN96N IN96P IN97N IN97P IN98N IN98P IN99N IN99P IN100N IN100P IN101N IN101P IN102N IN102P IN103N IN103P IN104N IN104P IN105N IN105P IN106N IN106P IN107N IN107P IN108N IN108P IN109N IN109P IN110N IN110P IN111N IN111P IN112N IN112P IN113N
Ball #
AB4 AB1 AB2 AA6 AA3 AA4 AA5 Y1 AA2 Y4 Y2 W1 Y3 W3 W2 W5 W4 V1 W6 U2 V4 U4 U3 U6 U5 T2 T1 T4 T3 R3 R2 R5 R4 P1 R6 P3 P2 N2 P4 N4 N3 M2 M1 M4 M3 M6
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OCX256 Crosspoint Switch--Advanced Datasheet
Table 21 Ball Name
IN113P IN114N IN114P IN115N IN115P IN116N IN116P IN117N IN117P IN118N IN118P IN119N IN119P IN120N IN120P IN121N IN121P IN122N IN122P IN123N IN123P IN124N IN124P IN125N IN125P IN126N IN126P IN127N IN127P NC NC NC OE# OUT00P OUT00N OUT01P OUT01N OUT02P OUT02N OUT03P OUT03N OUT04P OUT04N OUT05P OUT05N OUT06P OUT06N
OCX256 Pinout By Ball Name (Continued) Ball # Ball Name
E19 B19 C19 D20 B20 A20 C20 E21 D21 A22 F21 C22 B22 A23 D22 C23 B23 E23 D23 A24 F23 C24 B24 B25 D24 D25 C25 F25 E25 B26 A26 D26 C26 B27 A27 D27 C27 F27 E27 B28 A28 D28 C28 C29 B29 E29 D29 OUT54P OUT54N OUT55P OUT55N OUT56P OUT56N OUT57P OUT57N OUT58P OUT58N OUT59P OUT59N OUT60P OUT60N OUT61P OUT61N OUT62P OUT62N OUT63P OUT63N OUT64P OUT64N OUT65P OUT65N OUT66P OUT66N OUT67P OUT67N OUT68P OUT68N OUT69P OUT69N OUT70P OUT70N OUT71P OUT71N OUT72P OUT72N OUT73P OUT73N OUT74P OUT74N OUT75P OUT75N OUT76P OUT76N OUT77P
Ball # Ball Name
M5 L2 L1 L4 L3 L6 L5 K2 K1 K4 K3 K6 K5 J3 J2 H1 J6 H3 H2 G2 H4 F1 G3 G5 G4 G6 F2 F3 E1 E34 D2 AT32 D34 C6 F7 A5 E7 B6 D7 C7 A6 D8 B7 B8 C8 F9 A8 OUT07P OUT07N OUT08P OUT08N OUT09P OUT09N OUT10P OUT10N OUT11P OUT11N OUT12P OUT12N OUT13P OUT13N OUT14P OUT14N OUT15P OUT15N OUT16P OUT16N OUT17P OUT17N OUT18P OUT18N OUT19P OUT19N OUT20P OUT20N OUT21P OUT21N OUT22P OUT22N OUT23P OUT23N OUT24P OUT24N OUT25P OUT25N OUT26P OUT26N OUT27P OUT27N OUT28P OUT28N OUT29P OUT29N OUT30P
Ball # Ball Name
D9 E9 B9 C9 D10 A9 B10 C10 F11 A10 D11 E11 C12 D12 A12 B12 E13 F13 C13 D13 A13 B13 C14 D14 A14 B14 E15 F15 C15 D15 D16 B15 B16 C16 F17 A16 D17 E17 B17 C17 D18 A17 B18 C18 F19 A18 D19 OUT30N OUT31P OUT31N OUT32P OUT32N OUT33P OUT33N OUT34P OUT34N OUT35P OUT35N OUT36P OUT36N OUT37P OUT37N OUT38P OUT38N OUT39P OUT39N OUT40P OUT40N OUT41P OUT41N OUT42P OUT42N OUT43P OUT43N OUT44P OUT44N OUT45P OUT45N OUT46P OUT46N OUT47P OUT47N OUT48P OUT48N OUT49P OUT49N OUT50P OUT50N OUT51P OUT51N OUT52P OUT52N OUT53P OUT53N
Ball # Ball Name
A30 F29 C30 B30 C31 B31 E31 D31 A32 F31 C32 B32 B33 D32 A34 C33 E33 D33 B35 B34 AW35 AU34 AR33 AP33 AU33 AV34 AV33 AT33 AU32 AW34 AW32 AV32 AR31 AP31 AU31 AT31 AP30 AV31 AT30 AR30 AV30 AU30 AP29 AW30 AT29 AR29 AV29 OUT77N OUT78P OUT78N OUT79P OUT79N OUT80P OUT80N OUT81P OUT81N OUT82P OUT82N OUT83P OUT83N OUT84P OUT84N OUT85P OUT85N OUT86P OUT86N OUT87P OUT87N OUT88P OUT88N OUT89P OUT89N OUT90P OUT90N OUT91P OUT91N OUT92P OUT92N OUT93P OUT93N OUT94P OUT94N OUT95P OUT95N OUT96P OUT96N OUT97P OUT97N OUT98P OUT98N OUT99P OUT99N OUT100P OUT100N
Ball #
AU29 AU28 AT28 AW28 AV28 AU27 AT27 AW27 AV27 AU26 AT26 AW26 AV26 AR25 AP25 AU25 AT25 AT24 AV25 AV24 AU24 AP23 AW24 AT23 AR23 AV23 AU23 AT22 AW23 AV22 AU22 AP21 AW22 AT21 AR21 AV21 AU21 AU20 AW20 AV20 AT20 AU19 AV19 AW18 AP19 AU18 AV18
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OCX256 Crosspoint Switch--Advanced Datasheet
Table 21 Ball Name
OUT101P OUT101N OUT102P OUT102N OUT103P OUT103N OUT104P OUT104N OUT105P OUT105N OUT106P OUT106N OUT107P OUT107N OUT108P OUT108N OUT109P OUT109N OUT110P OUT110N OUT111P OUT111N OUT112P OUT112N OUT113P OUT113N OUT114P OUT114N OUT115P OUT115N OUT116P OUT116N OUT117P OUT117N OUT118P OUT118N OUT119P OUT119N OUT120P OUT120N OUT121P OUT121N OUT122P OUT122N OUT123P OUT123N OUT124P
OCX256 Pinout By Ball Name (Continued) Ball # Ball Name
E26 E28 E30 E32 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 F32 F34 H5 H6 H34 H35 M34 M35 P5 P6 P34 P35 T5 T6 T34 T35 V5 V6 V34 V35 Y5 Y6 Y34 Y35 AB5 AB6 AB34 AB35 AD5 AD6 VDD.CORE VDD.CORE VDD.CORE VDD.CORE VDD.CORE VDD.CORE VDD.CORE VDD.CORE VDD.CORE VDD.CORE VDD.CORE VDD.CORE VDD.CORE VDD.CORE VDD.CORE VDD.CORE VDD.CORE VDD.CORE VDD.CORE VDD.CORE VDD.CORE VDD.CORE VDD.CORE VDD.CORE VDD.CORE VDD.CORE VDD.CORE VDD.CORE VDD.CORE VDD.CORE VDD.CORE VDD.CORE VDD.CORE VDD.CORE VDD.CORE VDD.CORE VDD.CORE VDD.CORE VDD.CORE VDD.CORE VDD.CORE VDD.CORE VDD.CORE VDD.CORE VDD.IN VDD.IN VDD.IN
Ball # Ball Name
AV17 AT18 AT17 AU17 AP17 AR17 AV16 AW16 AT16 AU16 AV15 AW15 AT15 AU15 AP15 AR15 AV14 AW14 AU13 AV13 AR13 AT13 AW12 AP13 AU12 AV12 AW11 AT12 AT11 AU11 AP11 AR11 AV10 AW10 AT10 AU10 AU9 AV9 AR9 AT9 AV8 AW8 AT8 AU8 AP8 AR8 AV7 OUT124N OUT125P OUT125N OUT126P OUT126N OUT127P OUT127N RCA0 RCA1 RCA2 RCA3 RCA4 RCA5 RCA6 RCB0 RCB1 RCB2 RCB3 RCB4 RCB5 RCB6 RC_CLK# RC_EN# RCI0 RCI1 RCI2 RCI3 RCO0 RCO1 RCO2 RCO3 RCO4 TCK TDI TDO TMS TRST# UPDATE# VDD.CORE VDD.CORE VDD.CORE VDD.CORE VDD.CORE VDD.CORE VDD.CORE VDD.CORE VDD.CORE
Ball # Ball Name
AW6 AT7 AU7 AW5 AR7 AV6 AP7 F36 F37 AP38 AP37 AR38 AT38 AP36 AR37 AU35 AR34 AV35 AV5 AU6 AU5 AR3 AP4 AT6 AR6 AV4 AT2 F33 B36 C34 C35 D6 F5 E2 C5 F4 E3 B4 E8 E10 E12 E14 E16 E18 E20 E22 E24 VDD.CORE VDD.CORE VDD.CORE VDD.CORE VDD.CORE VDD.CORE VDD.CORE VDD.CORE VDD.CORE VDD.CORE VDD.CORE VDD.CORE VDD.CORE VDD.CORE VDD.CORE VDD.CORE VDD.CORE VDD.CORE VDD.CORE VDD.CORE VDD.CORE VDD.CORE VDD.CORE VDD.CORE VDD.CORE VDD.CORE VDD.CORE VDD.CORE VDD.CORE VDD.CORE VDD.CORE VDD.CORE VDD.CORE VDD.CORE VDD.CORE VDD.CORE VDD.CORE VDD.CORE VDD.CORE VDD.CORE VDD.CORE VDD.CORE VDD.CORE VDD.CORE VDD.CORE VDD.CORE VDD.CORE
Ball # Ball Name
AD34 AD35 AF5 AF6 AF34 AF35 AH5 AH6 AH34 AH35 AK5 AK6 AK34 AK35 AM5 AM6 AM34 AM35 AP5 AP6 AP10 AP12 AP14 AP16 AP18 AP20 AP22 AP24 AP26 AP28 AP32 AP34 AP35 AR10 AR12 AR14 AR16 AR18 AR20 AR22 AR24 AR26 AR28 AR32 N6 N5 G36 VDD.IN VDD.IN VDD.IN VDD.IN VDD.IN VDD.IN VDD.IN VDD.IN VDD.IN VDD.IN VDD.IN VDD.IN VDD.IN VDD.PAD VDD.PAD VDD.PAD VDD.PAD VDD.PAD VDD.PAD VDD.PAD VDD.PAD VDD.PAD VDD.PAD VDD.PAD VDD.PAD VDD.PAD VDD.PAD VDD.PAD VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
Ball #
J4 J5 L39 M36 V2 V3 Y36 Y39 AF4 AG2 AL37 AL38 AR2 A31 B5 B11 B21 C11 C21 D30 AP9 AP27 AR19 AR27 AT14 AT19 AT34 AU14 A1 A2 A3 A4 A7 A11 A15 A19 A21 A25 A29 A33 A35 A36 A37 A38 A39 B1 B2
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OCX256 Crosspoint Switch--Advanced Datasheet
Table 21 Ball Name
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
OCX256 Pinout By Ball Name (Continued) Ball # Ball Name Ball # Ball Name Ball #
Ball # Ball Name
B3 B37 B38 B39 C1 C2 C3 C4 C36 C37 C38 C39 D1 D3 D4 D5 D35 D36 D37 D39 E4 E5 E35 E36 G1 J1 J39 N1 N39 R1 U1 U39 W39 AA1 AA39 AC39 AE1 AE39 AG6 AG39 AJ6 AJ39 AL6 AN1 AN39 AR1 AR4 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
Ball # Ball Name
AR5 AR35 AR36 AT1 AT3 AT4 AT5 AT35 AT36 AT37 AT39 AU1 AU2 AU3 AU4 AU36 AU37 AU38 AU39 AV1 AV2 AV3 AV11 AV36 AV37 AV38 AV39 AW1 AW2 AW3 AW4 AW7 AW9 AW13 AW17 AW19 AW21 AW25 AW29 AW31 AW33 AW36 AW37 AW38 AW39
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OCX256 Crosspoint Switch--Advanced Datasheet
5.4 Package Dimensions
Figure 18 OCX256 Package--Bottom View
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Fairchild Semiconductor
OCX256 Crosspoint Switch--Advanced Datasheet
Figure 19 OCX256 Package--Top and Side Views
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41
OCX256 Crosspoint Switch--Advanced Datasheet
5.5 Package Thermal Characteristics
Table 22 Package TBGA NOTE:
1. Thermal performance values are based on simulation data.
Package Thermal Coefficients Pin Count 792
JC(C/W) JA(C/W) Still Air
0.4
7.58C/W
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OCX256 Crosspoint Switch--Advanced Datasheet 6. Power Consumption
Chip power consists of three integral elements (refer to Figure 20): 1. Input Power--This element has two components:
* *
a steady state component that is always ON, and a component that is based on the number of inputs being used.
2. Core Power--Core power is a function of data rate (Mb/s) and the number of connection paths through the switch matrix. 3. Output Power--This element is a fixed amount for each differential output. The value is zero if the Output Enable (OE#) is disabled or set to OFF. The following diagram shows the chip power elements (as described above), the formulas used for determining chip power, and the total power consumption as determined by the formula.
6.1 Power for OCX256L (LVDS)
Input Power
(always ON)
Core Power
Output Power
Switch Matrix OE#
Output Buffer
(512mW + 6.5mW/Input
+
0.015mW/Mbs/Connection
+
20mW/Output
Example: Worst Case = (512mW + 832mW) + (0.015 mW x 667 x 128) + (20mW x 128) 1344mW
+
1280mW
+
2560mW
= 5.18 watts
Figure 20 Power Consumption Diagram for the OCX256L using LVDS
Fairchild Semiconductor
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43
OCX256 Crosspoint Switch--Advanced Datasheet
6.2 Power for OCX256P (LVPECL)
Input Power
(always ON)
Core Power
Output Power
Switch Matrix OE#
Output Buffer
512mW + 10mW/Input
+
0.015mW/Mbs/Connection
+
37mW/Output
Example: Worst Case = (512mW + 1280mW) + (0.015 mW x 667 x 128) + (37mW x 128) 1792mW
+
1280mW
+
4736mW
= 7.81 watts
Figure 21 Power Consumption Diagram for the OCX256P using LVPECL
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[Rev. 2.0] 3/21/02
Fairchild Semiconductor
OCX256 Crosspoint Switch--Advanced Datasheet 7. Component Availability and Ordering Information
OCXxxxx - PPT
Family # I/O Ports I/O
L = LVDS P = LVPECL
Package Code
TB792 = 792 Pin Thin Ball Grid Array
Temperature Range
Blank - Commercial (0C to 70C) I - Industrial (-40C to +85C)
8. Glossary
CLOCK: A single differential input used to gate data into registers in the Output Buffer. The input serves all outputs of the OCX. The neighbor input can also be used as a register clock. CROSSPOINT: A single cell controlled by two RAM bits. The RAM bits are connected in a master-slave configuration to provide an update for programming and changing program information all at once. CROSSPOINT ARRAY: An array of Crosspoint cells used to connect any input port to any output port. INPUT OR OUTPUT PATH: The signal flow from pin to array and array to pin. Each path has a register with selectable clocks, drivers for the loaded outputs with selectable enables, and sense circuits to detect changes on either side of the IO Buffer. NEXT NEIGHBOR: A physically adjacent port can be used as a clock source for an output configured in registered mode. These outputs are grouped in pairs such that the signal being switched through Output 0 can be used to clock the signal being switched through Output 1, or vice-versa. Any single clock or data input signal can be used to clock any other input signal provided they are switched to an appropriate output pair. PORT: A name followed by a number to identify a pin on the device. RAPIDCONFIGURE: A parallel programming method for the OCX devices. The RC mode uses 25 dedicated pins to program the Crosspoint Array and the IO Buffers. The 25 pins consist of an enable, a clock, four instruction bits, two seven-bit address fields, and a five-bit data field.
Fairchild Semiconductor
[Rev. 2.0] 3/21/02
45
OCX256 Crosspoint Switch--Advanced Datasheet
Revision History
Date 9/25/2000 10/8/00 Version No. Revision 1.0 Revision 1.1 Description Preliminary release of "Advanced" datasheet Additions include RCO output pin information, pinout drawing, pinout tables, package dimensions and illustration, duty-cycle diagram, thermal characteristics table, device reset options table, a section on configuring multiple devices, bitstream generation and downloading, JTAG information, and Power Consumption information/illustrations. Corrections made to pinout drawing and pin names. Updated RapidConfigure Read Cycle timing diagram so that RCO is relative to RC_CLK#; RCO was previously relative to RC_EN#. Replaced "+" on signal names to "P" and "-" to "N". Corrected RCO[4:0] pin locations. Corrected pin names ENAB, RCC, and RCE on Pinout drawing and tables to be OE#, RC_CLK#, and RC_EN# respectively; corrections to Input and Output pin names 59P, 60P, 61P, and 62P in tables 22 and 23. Corrected pin names in Table 22 "Pinout By Ball Sequence": To From B32 OUT58P B32 OUT59P C33 OUT60P C33 OUT61P D32 OUT59P D32 OUT60P D33 OUT61P D33 OUT62P AR9 OUT120P AR9 OUT120N AT9 OUT120N AT9 OUT120P Reversed "input" and "output" descriptions in Table 3 "RapidConfigure Programming Instructions" for instructions 0101, 0111, 1000, 1001, and 1010. Corrected pin names in Table 22 "Pinout By Ball Sequence": To From K5 IN119N K5 IN119P K6 IN119P K6 IN119N AM38 IN597P AM38 IN59P AU9 OUT119P AU9 OUT119N AV9 OUT119N AV9 OUT119P Changed the VIH, VIL, VOH, and VOL minimum and maximum values for LVPECL DC specifications in Table 20; added a note below table explaining the current values; changed Pass Transistor to high-performance buffering circuit; updated power and ground pin count in Table 12. Created separate parts for LVDS and LVPECL (OCX256L and OCX256P respectively); created new LVDS and LVPECL signal drawings; created new LVDS and LVPECL power consumption drawings; updated DC electrical specifications tables; changes/corrections to LVDS and LVPECL DC Electrical Specs tables. Changes to LVDS and LVPECL power consumption diagrams and Input power specs. Changes to LVDS and LVPECL DC Electrical specs tables; added termination impedance values Added jitter specifications and PRBS Data Eye diagram. Swapped Ball Name(s) OUT*P to OUT*N on pinout drawing and tables--Ball Numbers remain the same.
11/1/00 11/16/00
Revision 1.2 Revision 1.3
11/21/00
Revision 1.4
1/12/01
Revision 1.5
2/20/01
Revision 1.6
4/5/01
Revision 1.7
5/21/2001 7/27/01 9/14/01 10/26/01
Revision 1.8 Revision 1.9 Revision 1.10 Revision 2.0
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Fairchild Semiconductor
OCX256 Crosspoint Switch--Advanced Datasheet 9. Product Status Definition
Datasheet Identification
Advanced
Product Status
Formative or In Design
Definition
This datasheet contains the design specifications for product development. Specification may change in any manner without notice. This datasheet contains the preliminary data, and supplementary data will be published at a later date. Fairchild reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This datasheet contains final specifications. Fairchild reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This datasheet contains specifications for a product that has been discontinued by Fairchild. The datasheet is provided for reference information only.
Preliminary
Preproduction Product
No Identification
Full Production
Obsolete
No longer in Production
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuity and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATIONS. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect is safety of effectiveness.
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Fairchild Semiconductor
[Rev. 2.0] 3/21/02
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