View 16V72TJ_963357.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Preliminary Spec.
MITSUBISHI LSIs
MH16V72TJ -6, -7
DESCRIPTION
The MH16V72TJ is 16777216-word x 72-bit dynamic ram module. This consist of eighteen industry standard 16M x 4 dynamic RAMs in TSOP and two industry standard input buffer in TSSOP. The mounting of TSOP on a card edge dual in-line package provides any application where high densities and large of quantities memory are required. This is a socket-type memory module ,suitable for easy interchange or addition of module.
Rev.3 '96.6.19
FAST PAGE MODE 1207959552 - BIT ( 16777216 - WORD BY 72 - BIT ) DYNAMIC RAM
PIN CONFIGURATION
85pin 94pin
1pin 10pin 11pin
FEATURES
Type name
MH16V72TJ-6 MH16V72TJ-7
/RAS /CAS Address /OE access access access access time time time time Cycle time Power dissipation
(typ.W) (max.ns) (max.ns) (max.ns) (max.ns) (min.ns)
95pin
60 70
20 25
35 40
20 25
110 130
5.1 4.4
Utilizes industry standard 16M x 4 RAMs TSOP and industry standard input buffer in TSSOP 168-pin (84-pin dual in-line package) Single +3.3V(0.3V) supply operation Low stand-by power dissipation . . . . . . . . 68.4mW(Max) Low operation power dissipation MH16V72TJ -6 . . . . . . . . . . . . . . . . . . 6.52W(Max) MH16V72TJ -7 . . . . . . . . . . . . . . . . . . 5.54W(Max) All input are directly TTL compatible All output are three-state and directory LVTTL compatible Includes(0.22uF x 20) decoupling capacitors 4096 refresh cycle every 64ms Fast page mode JEDEC standard pin configuration & Buffered PD pin Buffered input except /RAS and DQ Gold plating contact pads
124pin BACK SIDE 125pin
40pin FRONT SIDE 41pin
APPLICATION
Main memory unit for computers , Microcomputer memory 168pin 84pin
PD&ID TABLE
-6 -7 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8 ID0 ID1 1 0 0 1 1 1 1 0 1 0 1 1 1 1 0 0 1 0 0 0
1 = drive to VOH , 0 = drive to VOL PD pin . . . buffered. When /PDE is low, PD information can be read ID pin . . . non-buffered
1
MITSUBISHI ELECTRIC
Preliminary Spec.
MITSUBISHI LSIs
MH16V72TJ -6, -7
PIN CONFIGURATION
Pin No.
Rev.3 '96.6.19
FAST PAGE MODE 1207959552 - BIT ( 16777216 - WORD BY 72 - BIT ) DYNAMIC RAM
Pin Name Vss DQ0 DQ1 DQ2 DQ3 Vcc DQ4 DQ5 DQ6 DQ7 DQ8 Vss DQ9 DQ10 DQ11 DQ12 DQ13 Vcc DQ14 DQ15 DQ16 DQ17 Vss Reserved Reserved Vcc /WE0 /CAS0 Reserved /RAS0 /OE0 Vss A0 A2 A4 A6 A8 A10 A12 Vcc RFU RFU
Pin No.
Pin Name Vss /OE2 /RAS2 /CAS4 Reserved /WE2 Vcc Reserved Reserved DQ18 DQ19 Vss DQ20 DQ21 DQ22 DQ23 Vcc DQ24 RFU RFU RFU RFU DQ25 DQ26 DQ27 Vss DQ28 DQ29 DQ30 DQ31 Vcc DQ32 DQ33 DQ34 DQ35 Vss PD1 PD3 PD5 PD7 ID0 Vcc
Pin No.
Pin Name Vss DQ36 DQ37 DQ38 DQ39 Vcc DQ40 DQ41 DQ42 DQ43 DQ44 Vss DQ45 DQ46 DQ47 DQ48 DQ49 Vcc DQ50 DQ51 DQ52 DQ53 Vss Reserved Reserved Vcc RFU Reserved Reserved Reserved RFU Vss A1 A3 A5 A7 A9 A11 Reserved Vcc RFU B0
Pin No.
Pin Name Vss RFU Reserved Reserved Reserved /PDE Vcc Reserved Reserved DQ54 DQ55 Vss DQ56 DQ57 DQ58 DQ59 Vcc DQ60 RFU RFU RFU RFU DQ61 DQ62 DQ63 Vss DQ64 DQ65 DQ66 DQ67 Vcc DQ68 DQ69 DQ70 DQ71 Vss PD2 PD4 PD6 PD8 ID1 Vcc
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84
85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126
127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168
Reserved: Reserved use RFU: Reserved for future use
2
MITSUBISHI ELECTRIC
Preliminary Spec.
MITSUBISHI LSIs
MH16V72TJ -6, -7
BLOCK DIAGRAM
/RAS0 /CAS0 /WE0 /OE0
/OE /W /CAS /RAS DQ1 ~DQ4
Rev.3 '96.6.19
FAST PAGE MODE 1207959552 - BIT ( 16777216 - WORD BY 72 - BIT ) DYNAMIC RAM
/RAS2 /CAS4 /WE2 /OE2
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35
PIN NAME /RAS0, /RAS2 /CAS0, /CAS2 /WE0, /WE2 /OE0, /OE2 A0~A12, B0 DQ0~DQ71 Vcc Vss /OE /OE /W /CAS /RAS DQ1 ~DQ4
DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DQ64 DQ65 DQ66 DQ67 DQ68 DQ69 DQ70 DQ71
M5M467400
D1 /OE /W /CAS
M5M467400
D10 /OE /W /CAS
/RAS DQ1 ~DQ4
/RAS DQ1 ~DQ4
M5M467400
D2 /OE /W /CAS
M5M467400
D11 /W /CAS
/RAS DQ1 ~DQ4
/RAS DQ1 ~DQ4
M5M467400
D3 /OE /W /CAS
M5M467400
D12 /OE /W /CAS
/RAS DQ1 ~DQ4
/RAS DQ1 ~DQ4
M5M467400
D4 /OE /W /CAS
M5M467400
D13 /OE /W /CAS
/RAS DQ1 ~DQ4
/RAS DQ1 ~DQ4
M5M467400
D5 /OE /W /CAS
M5M467400
D14 /OE /W /CAS
/RAS DQ1 ~DQ4
/RAS DQ1 ~DQ4
M5M467400
D6 /OE /W /CAS
M5M467400
D15 /OE /W /CAS
/RAS DQ1 ~DQ4
/RAS DQ1 ~DQ4
M5M467400
D7 /OE /W /CAS
M5M467400
D16 /OE /W /CAS
/RAS DQ1 ~DQ4
/RAS DQ1 ~DQ4
M5M467400
D8 /OE /W /CAS
M5M467400
D17 /OE /W /CAS
/RAS DQ1 ~DQ4
/RAS DQ1 ~DQ4
M5M467400
D9
M5M467400
D18
A0 B0 A1~A12
D1~D9 D10~D18 D1~D18
Vcc Vss
C1~C20 ...
D1~D18 & INPUT BUFFER
FUNCTION ROW ADDRESS STROBE INPUT COLUMN ADDRESS STROBE INPUT WRITE CONTROL INPUT OUTPUT ENABLE INPUT ADDRESS INPUT DATA I/O POWER SUPPLY GROUND
3
MITSUBISHI ELECTRIC
Preliminary Spec.
MITSUBISHI LSIs
MH16V72TJ -6, -7
FUNCTION
The MH16V72TJ provide, in addition to normal read, write, and read-modify-write operations, a number of other functions, e.g., Fast page mode, /RASonly refresh, and delayed-write. The input conditions for each are shown in Table 1.
Rev.3 '96.6.19
FAST PAGE MODE 1207959552 - BIT ( 16777216 - WORD BY 72 - BIT ) DYNAMIC RAM
Table 1 Input conditions for each mode
Inputs Operation /RAS Read Write (Early write) Write (Delayed write) Read-modify-write /RAS-only refresh Hidden refresh /CAS before /RAS refresh Standby ACT ACT ACT ACT ACT ACT ACT NAC /CAS ACT ACT ACT ACT NAC ACT ACT DNC /W NAC ACT ACT ACT DNC DNC NAC DNC /OE ACT DNC DNC ACT DNC ACT DNC DNC Row address APD APD APD APD APD APD DNC DNC Column address APD APD APD APD DNC DNC DNC DNC Input/Output Refresh Input OPN VLD VLD VLD DNC OPN DNC DNC Output VLD OPN IVD VLD OPN VLD OPN OPN YES YES YES YES YES YES YES NO Hyper page mode identical Remark
Note : ACT : active, NAC : nonactive, DNC : don' t care, VLD : valid, IVD : Invalid, APD : applied, OPN : open
4
MITSUBISHI ELECTRIC
Preliminary Spec.
MITSUBISHI LSIs
MH16V72TJ -6, -7
ABSOLUTE MAXIMUM RATINGS
Symbol Vcc VI VO IO Pd Topr Tstg Parameter Supply voltage Input voltage Output voltage Output current Power dissipation Operating temperature Storage temperature Conditions With respect to Vss Ratings -0.5~4.6 -0.5~Vcc+0.5 -0.5~Vcc+0.5 50 20 0~70 -40~100
Rev.3 '96.6.19
FAST PAGE MODE 1207959552 - BIT ( 16777216 - WORD BY 72 - BIT ) DYNAMIC RAM
Unit V mA W C C
Ta=25C
RECOMMENDED OPERATING CONDITIONS
Symbol Vcc Vss VIH VIL Parameter Supply voltage Supply voltage High-level input voltage, all inputs Low-level input voltage Min 3.0 0 2.0 -0.3
(Ta=0~ 70C, unless otherwise noted) (Note 1)
Limits Nom 3.3 0
Max 3.6 0
Vcc+0.3
Unit V V V V
0.8
Note 1 : All voltage values are with respect to Vss
ELECTRICAL CHARACTERISTICS
Symbol VOH VOL IOZ II I I (RAS) ICC1 (AV) Parameter High-level output voltage Low-level output voltage Off-state output current Input current (except /RAS) Input current (/RAS) Average supply current from Vcc operating
(Ta=0~ 70C, Vcc=3.3V0.3V, Vss=0V, unless otherwise noted) (Note 2)
Test conditions IOH=-2mA IOL=2mA Q floating 0VVOUTVcc
0VVINVcc+0.3, Other input pins=0V 0VVINVcc+0.3, Other input pins=0V
Min 2.4 0 -10 -10 -90
Limits Typ
Max Vcc 0.4 10 10 90 1810
Unit V V uA uA uA mA
-6 -7
(Note 3,4,5)
/RAS, /CAS cycling tRC=tWC=min. output open /RAS=/CAS =VIH, output open /RAS=/CASVcc -0.2, output open /RAS=VIL,/CAS cycling tPC=min. output open /CAS before /RAS refresh cycling tRC=min. output open
1540 28 19 1720 1450 1980 1620 mA mA mA
ICC2
Supply current from Vcc , stand-by Average supply current from Vcc Fast-Page-Mode
-6
(Note 3,4,5)
ICC4(AV)
-7 -6 -7
ICC6(AV)
Average supply current from Vcc /CAS before /RAS refresh mode
(Note 3,5)
Note 2: Current flowing into an IC is positive, out is negative. 3: Icc1 (AV), Icc3 (AV), Icc4 (AV) and Icc6 (AV) are dependent on cycle rate. Maximum current is measured at the fastest cycle rate. 4: Icc1 (AV) and Icc4 (AV) are dependent on output loading. Specified values are obtained with the output open. 5: Under condition of colmun address being changed once or less while /RAS=VIL and /CAS=VOH
CAPACITANCE
Symbol
(Ta = 0A70Ae, Vcc = 3.3VA}0.3V, Vss = 0V, unless otherwise noted)
Parameter
Test conditions VI=Vss f=1MHZ Vi=25mVrms
Min
Limits Typ
CI (/RAS) Input capacitance, /RAS input CI Input capacitance, except /RAS input C(DQ) Input/Output capacitance,DATA
Max 70 11 14
Unit pF pF pF
5
MITSUBISHI ELECTRIC
Preliminary Spec.
MITSUBISHI LSIs
MH16V72TJ -6, -7
SWITCHING CHARACTERISTICS
Symbol tCAC tRAC tAA tCPA tOEA tCLZ tOFF tOEZ
(Ta=0~70C, Vcc=3.3V0.3V, Vss=0V, unless otherwise noted , see notes 6,14,15)
Rev.3 '96.6.19
FAST PAGE MODE 1207959552 - BIT ( 16777216 - WORD BY 72 - BIT ) DYNAMIC RAM
Limits Parameter Min Access time from /CAS Access time from /RAS Columu address access time Access time from /CAS precharge Access time from /OE Output low impedance time from /CAS low Output disable time after /CAS high Output disable time after /OE high
(Note 7,8) (Note 7,9) (Note 7,10) (Note 7,11) (Note 7) (Note 7) (Note 12) (Note 12)
-6 Max 20 60 35 40 20 10 5 5 20 20 10 5 5 Min
-7 Max 25 70 40 45 25 25 25
Unit ns ns ns ns ns ns ns ns
Note 6: An initial pause of 500us is required after power-up followed by a minimum of eight initialization cycles (any combination of cycles containing a /RAS clock such as /RAS-Only refresh). Note the /RAS may be cycled during the initial pause . And any 8 /RAS or /RAS /CAS cycles are required after prolonged periods (greater than 64 ms) of /RAS inactivity before proper device operation is achieved. 7: Measured with a load circuit equivalent to 1TTL loads and 50pF. The reference levels for measuring of output signals are 2.0(VOH)and 0.8(VOL). 8: Assumes that tRCDtRCD(max), tASCASC(max). 9: Assumes that tRCDtRCD(max) and tRADtRAD(max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, tRAC will increase by amount that tRCD exceeds the value shown. 10: Assumes that tRADtRAD(max) and tASCtASC(max). 11: Assumes that tCPtCP(max) and tASCtASC(max). 12: tOEZ (max) and tOFF(max) defines the time at which the output achieves the high impedance state (IOUT I10uAI) and is not reference to VOH(min) or VOL(max).
TIMING REQUIREMENTS (For Read, Write, Read-Modify-Write ,Refresh, and Fast-Page Mode Cycles)
(Ta=0~70C, Vcc=3.3V0.3V, Vss=0V, unless otherwise noted ,see notes 14,15)
Limits Symbol tREF tRP tRCD tCRP tRPC tCPN tRAD tASR tASC tRAH tCAH tDZC tDZO tCDD tODD tT Parameter Min Refresh cycle time /RAS high pulse width Delay time, /RAS low to /CAS low Delay time, /CAS high to /RAS low Delay time, /RAS high to /CAS low /CAS high pulse width Column address delay time from /RAS low Row address setup time before /RAS low Column address setup time before /CAS low Row address hold time after /RAS low Column address hold time after /CAS low Delay time, data to /CAS low Delay time, data to /OE low Delay time, /CAS high to data Delay time, /OE high to data Transition time 40 18 15 -5 10 13 5 0 8 10 0 0 20 20 1 -6 Max 64 40 Min 50 18 15 -5 10 13 5 0 8 17 0 0 25 25 1 -7 Max 64 45 Unit ms ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
(Note15)
(Note16) (Note17)
24 10
29 10
(Note18) (Note18) (Note19) (Note19) (Note20)
50
50
Note 13: The timing requirements are assumed tT =5ns. 14: VIH(min) and VIL(max) are reference levels for measuring timing of input signals. 15: tRCD(max) is specified as a reference point only. If tRCD is less than tRCD(max), access time is tRAC. If tRCD is greater than tRCD(max), access time is controlled exclusively by tCAC or tAA. . 16: tRAD(max) is specified as a reference point only. If tRADtRAD(max) and tASCtASC(max), access time is controlled exclusively by tAA. 17: tASC(max) is specified as a reference point only. If tRCDtRCD(max) and tASCtASC(max), access time is controlled exclusively by tCAC. 18: Either tDZC or tDZO must be satisfied. 19: Either tRDD or tCDD or tODD must be satisfied. 20: tT is measured between VIH(min) and VIL(max).
6
MITSUBISHI ELECTRIC
Preliminary Spec.
MITSUBISHI LSIs
MH16V72TJ -6, -7
Read and Refresh Cycles
Limits Symbol tRC tRAS tCAS tCSH tRSH tRCS tRCH tRRH tRAL tORH tOCH Parameter Min Read cycle time /RAS iow pulse width /CAS iow pulse width /CAS hold time after /RAS iow /RAS hold time after /CAS iow Read Setup time after /CAS high Read hold time after /CAS iow Read hold time after /RAS iow Column address to /RAS hold time /RAS hold time after /OE iow /CAS hold time after /OE iow 110 60 15 58 20 0 0 3 35 20 15 -6 Max 10000 10000 Min 130 70 20 68 25 0 0 3 40 25 20 -7 Max 10000 10000 ns ns ns ns ns ns ns ns ns ns ns
Rev.3 '96.6.19
FAST PAGE MODE 1207959552 - BIT ( 16777216 - WORD BY 72 - BIT ) DYNAMIC RAM
Unit
(Note 21) (Note 21)
Note 21: Either tRCH or tRRH must be satisfied for a read cycle.
Write Cycle (Early Write and Delayed Write)
Limits Symbol tWC tRAS tCAS tCSH tRSH tWCS tWCH tCWL tRWL tWP tDS tDH tOEH Parameter Write cycle time /RAS iow pulse width /CAS iow pulse width /CAS hold time after /RAS iow /RAS hold time after /CAS low Write setup time before /CAS low Write hold time after /CAS low /CAS hold time after /W low /RAS hold time after W low Write pulse width Data setup time before /CAS low or W low Data hold time after /CAS low or W low /OE hold time after /W low Min 110 60 15 55 20 0 10 15 20 10 -2 17 15 -6 Max 10000 10000 Min 130 70 20 65 25 0 15 20 25 15 -2 20 20 -7 Max 10000 10000 ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
(Note 23)
Read-Write and Read-Modify-Write Cycles
Limits Symbol tRWC tRAS tCAS tCSH tRSH tRCS tCWD tRWD tAWD tCWL tRWL tWP tDS tDH tOEH Parameter Read write/read modify write cycle time /RAS low pulse width /CAS low pulse width /CAS hold time after /RAS low /RAS hold time after /CAS low Read setup time before /CAS low Delay time, /CAS low to /W low Delay time, /RAS low to /W low Delay time, address to /W low /CAS hold time after /W low /RAS hold time after /W low Write pulse width Data setup time before /CAS low or /W low Data hold time after /CAS low or /W low OE hold time after W low
(Note22)
-6 Min 150 95 50 90 55 0 30 70 45 15 20 10 -2 15 15 Max 10000 10000 Min 180 115 65 110 70 0 40 85 55 20 25 15 -2 15 15
-7 Max 10000 10000
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
(Note23) (Note23) (Note23)
Note 22: tRWC is specified as tRWC(min)=tRAC(max)+tODD(min)+tRWL(min)+tRP(min)+4tT. 23:tWCS, tCWD,tRWD ,tAWD and,tCPWD are specified as reference points only. If tWCStWCS(min) the cycle is an early write cycle and the DQ pins will remain high impedance throughout the entire cycle. If tCWDtCWD(min), tRWDtRWD (min), tAWDtAWD(min) and tCPWD tCPWD(min) (for Fast page mode cycle only), the cycle is a read-modify-write cycle and the DQ will contain the data read from the selected address. If neither of the above condition (delayed write) of the DQ (at access time and until /CAS or /OE goes back to VIH) is indeteminate.
7
MITSUBISHI ELECTRIC
Preliminary Spec.
MITSUBISHI LSIs
MH16V72TJ -6, -7
Fast Page Mode Cycle (Read, Early Write, Read -Write, Read-Modify-Write Cycle) (Note 25)
Limits Symbol tPC tPRWC tRAS tCP tCPRH tCPWD Parameter Fast page mode read/write cycle time
Fast page mode read write/read modify write cycle time
Rev.3 '96.6.19
FAST PAGE MODE 1207959552 - BIT ( 16777216 - WORD BY 72 - BIT ) DYNAMIC RAM
-6 Min 40 75 100 10 40 35 Max Min 45 90 115 10 45 40
-7 Max
Unit ns ns ns ns ns ns
/RAS low pulse width for read write cycle /CAS high pulse width /RAS hold time after /CAS precharge Delay time, /CAS precharge to W low
(Note25) (Note26) (Note23)
100000 15
100000 15
Note 24: All previously specified timing requirements and switching characteristics are applicable to their respective Fast page mode cycle. 25: tRAS(min) is specified as two cycles of /CAS input are performed. 26: tCP(max) is specified as a reference point only.
/CAS before /RAS Refresh Cycle (Note 27)
Limits Symbol tCSR tCHR tRSR tRHR Parameter /CAS setup time before /RAS low /CAS hold time after /RAS low Read setup time before /RAS low Read hold time after /RAS low Min 14 7 15 5 -6 Max Min 14 12 15 10 -7 Max ns ns ns ns Unit
Note 27: Eight or more /CAS before /RAS cycles instead of eight /RAS cycles are necessary for proper operation of /CAS before /RAS refresh mode.
8
MITSUBISHI ELECTRIC
Preliminary Spec.
MITSUBISHI LSIs
MH16V72TJ -6, -7
Rev.3 '96.6.19
FAST PAGE MODE 1207959552 - BIT ( 16777216 - WORD BY 72 - BIT ) DYNAMIC RAM
Timing Diagrams Read Cycle
(Note 28)
tRC tRAS VIH RAS VIL tCSH tCRP VIH CAS VIL tASR VIH
A0/B0-A12
tRP
tRCD
tRSH tCAS
tRPC
tCRP
tRAD tRAH tASC tCAH
COLUMN ADDRESS A0-A11
tRAL tCPN
tASR
VIL
ROW ADDRESS A0-A11
ROW ADDRESS
tRRH tRCS VIH W VIL tDZC VIH Hi-Z VIL tCAC tAA tCLZ
DQ (OUTPUTS)
tRCH
tCDD
DQ (INPUTS)
tOFF
VOH Hi-Z VOL tRAC tDZO VIH VIL
tORH DATA VALID
Hi-Z
tOEZ tOEA tOCH tODD
Note 28
Indicates the don't care input. VIH(min)AOVINAOVIH(max) or VIL(min)AOVINAOVIL(max) Indicates the invalid output.
9
MITSUBISHI ELECTRIC
Preliminary Spec.
MITSUBISHI LSIs
MH16V72TJ -6, -7
Write Cycle (Early write)
tWC tRAS VIH VIL tCSH tCRP VIH VIL tASR VIH
A0/B0-A12
Rev.3 '96.6.19
FAST PAGE MODE 1207959552 - BIT ( 16777216 - WORD BY 72 - BIT ) DYNAMIC RAM
tRP
RAS
tRCD
tRSH tCAS
tRPC
tCRP
CAS
tASR tRAH tASC tCAH
COLUMN ADDRESS A0/B0-A10 ROW ADDRESS
VIL
ROW ADDRESS A0/B0-A10
tWCS W VIH VIL tDS VIH VIL
tWCH
tDH
DQ (INPUTS)
DATA VALID
DQ (OUTPUTS)
VOH Hi-Z VOL
OE
VIH VIL
10
MITSUBISHI ELECTRIC
Preliminary Spec.
MITSUBISHI LSIs
MH16V72TJ -6, -7
Rev.3 '96.6.19
FAST PAGE MODE 1207959552 - BIT ( 16777216 - WORD BY 72 - BIT ) DYNAMIC RAM
Write Cycle (Delayed write)
tWC tRAS VIH RAS VIL tCSH tCRP VIH CAS VIL tASR tRAH tASC tCAH tASR
ROW ADDRESS
tRP
tRCD
tRSH tCAS
tRPC
tCRP
VIH
A0/B0-A12
VIL
ROW ADDRESS A11
COLUMN ADDRESS
tCWL tRCS VIH W VIL tWCH tDZC
DQ (INPUTS)
tRWL tWP
tDS Hi-Z tCLZ
tDH
DATA VALID
VIH VIL
DQ (OUTPUTS)
VOH Hi-Z VOL tDZO tOEZ tODD tOEH Hi-Z
OE
VIH VIL
11
MITSUBISHI ELECTRIC
Preliminary Spec.
MITSUBISHI LSIs
MH16V72TJ -6, -7
Rev.3 '96.6.19
FAST PAGE MODE 1207959552 - BIT ( 16777216 - WORD BY 72 - BIT ) DYNAMIC RAM
Read-Write, Read-Modify-Write Cycle
tRWC tRAS VIH VIL tCSH tCRP VIH CAS VIL tASR tRAH tRAD tASC tCAH tASR tRCD tRSH tCAS tRPC tCRP tRP
RAS
VIH
A0/B0-A12
VIL
ROW ADDRESS A0/B0-A10
COLUMN ADDRESS A0/B0-A10
ROW ADDRESS
tRCS VIH VIL
tAWD tCWD tRWD
tCWL tRWL tWP
W
tDS tDZC
DQ (INPUTS)
tDH
VIH VIL tCAC tAA tCLZ
Hi-Z
DATA VALID
DQ (OUTPUTS)
VOH Hi-Z VOL tRAC tDZO VIH VIL tOEA
DATA VALID
Hi-Z tODD tOEZ tOEH
OE
12
MITSUBISHI ELECTRIC
Preliminary Spec.
MITSUBISHI LSIs
MH16V72TJ -6, -7
Rev.3 '96.6.19
FAST PAGE MODE 1207959552 - BIT ( 16777216 - WORD BY 72 - BIT ) DYNAMIC RAM
RAS-only Refresh Cycle
tRC tRAS RAS VIH VIL tRPC tCRP CAS VIH VIL tASR tRAH tASR tCRP tRP
VIH
A0/B0-A12
VIL
ROW ADDRESS
ROW ADDRESS
W
VIH VIL
DQ (INPUTS)
VIH VIL
DQ (OUTPUTS)
VOH VOL
Hi-Z
VIH OE VIL
13
MITSUBISHI ELECTRIC
Preliminary Spec.
MITSUBISHI LSIs
MH16V72TJ -6, -7
CAS before RAS Refresh Cycle
Rev.3 '96.6.19
FAST PAGE MODE 1207959552 - BIT ( 16777216 - WORD BY 72 - BIT ) DYNAMIC RAM
tRC tRP VIH RAS VIL tCSR tRAS tRAS
tRC tRP
tRPC VIH CAS VIL
tCHR
tRPC
tCSR
tCHR
tRPC
tCRP
tCPN tASR VIH
A0/B0-A12 ROW ADDRESS COLUMN ADDRESS
VIL tRCH tRSR VIH tRHR tRSR tRHR
tRCS
W VIL
DQ (INPUTS)
VIH VIL tOFF
DQ (OUTPUTS)
VOH VOL tOEZ VIH
Hi-Z
OE
VIL
14
MITSUBISHI ELECTRIC
Preliminary Spec.
MITSUBISHI LSIs
MH16V72TJ -6, -7
Rev.3 '96.6.19
FAST PAGE MODE 1207959552 - BIT ( 16777216 - WORD BY 72 - BIT ) DYNAMIC RAM
Hidden Refresh Cycle (Read)
(Note 29)
tRC tRAS VIH RAS VIL tCRP VIH CAS VIL tRAD tASR VIH
A0/B0-A12
tRC tRP tRAS tRP
tRCD
tRSH
tCHR
tRAH
ROW ADDRESS A11
tASC
tCAH
COLUMN ADDRESS
tASR
VIL
ROW ADDRESS
tRCS tRAL VIH W VIL tDZC tCDD tRRH
DQ (INPUTS)
VIH Hi-Z VIL tCAC tAA tCLZ Hi-Z VOL tRAC tDZO VIL tOEA tORH tOEZ tODD
DATA VALID
tOFF
DQ (OUTPUTS)
VOH Hi-Z
OE
VIH
Note 29: Early write, delayed write, read write or read modify write cycle is applicable instead of read cycle. Timing requirements and output state are the same as that of each cycle shown above.
15
MITSUBISHI ELECTRIC
Preliminary Spec.
MITSUBISHI LSIs
MH16V72TJ -6, -7
Fast Page Mode Read Cycle
Rev.3 '96.6.19
FAST PAGE MODE 1207959552 - BIT ( 16777216 - WORD BY 72 - BIT ) DYNAMIC RAM
tRAS VIH RAS VIL tCSH tCRP VIH CAS VIL tRAD tASR VIH
A0/B0-A12
tRP
tPC tCAS tCP tCAS tCP
tRCD
tRSH tCAS
tCPRH tASC tCAH
COLUMN-1
tRAH
tASC
tCAH
tASC
tCAH
tASR
ROW ADDRESS
ROW ADDRESS
COLUMN-2
COLUMN-3
VIL
A11
tRAL tRCS VIH W VIL tDZC tDZC tDZC tRCH tRCS tRCH tRCS tRRH
tRCH
tCDD
DQ (INPUTS)
VIH Hi-Z VIL tCAC tAA tCLZ tOFF tAA tCLZ
DATA VALID-1 DATA VALID-2
Hi-Z tCAC tOFF tCAC tAA tCLZ
DATA VALID-3
tOFF
DQ (OUTPUTS)
VOH Hi-Z VOL tRAC tDZO VIL
tCPA tOEA tOCH tOEZ tOEA tOCH
tCPA tOEZ tOEA tOCH tOEZ
OE
VIH tDZO tODD tODD tDZO tORH tODD
16
MITSUBISHI ELECTRIC
Preliminary Spec.
MITSUBISHI LSIs
MH16V72TJ -6, -7
Rev.3 '96.6.19
FAST PAGE MODE 1207959552 - BIT ( 16777216 - WORD BY 72 - BIT ) DYNAMIC RAM
Fast Page Mode Write Cycle (Early Write)
tRAS VIH RAS VIL tCSH tCRP VIH CAS VIL tASR tRAH tASC tCAH tASC tCAH tASC tCAH tRCD tCAS tCP tPC tCAS tCP tRSH tCAS
tRP
tASR
ROW ADDRESS
VIH
A0/B0-A12
VIL
ROW ADDRESS A11
COLUMN-1
COLUMN-2
COLUMN-3
tWCS VIH W VIL tDS
DQ (INPUTS)
tWCH
tWCS
tWCH
tWCS
tWCH
tDH
DATA VALID-1
tDS
tDH
tDS
tDH
DATA VALID-3
VIH VIL
DATA VALID-2
DQ (OUTPUTS)
VOH Hi-Z VOL
OE
VIH VIL
17
MITSUBISHI ELECTRIC
Preliminary Spec.
MITSUBISHI LSIs
MH16V72TJ -6, -7
Rev.3 '96.6.19
FAST PAGE MODE 1207959552 - BIT ( 16777216 - WORD BY 72 - BIT ) DYNAMIC RAM
Fast-Page Mode Write Cycle (Delayed Write)
tRAS VIH RAS VIL tCSH tCRP VIH CAS VIL tASR tRAH tASC tCAH tASC tCAH tRWL tCWL tRCD tCAS tCP tRSH tPC tCAS
tRP
tASR
ROW ADDRESS
VIH
A0/B0-A12
VIL
ROW ADDRESS A11
COLUMN-1
COLUMN-2
tRCS VIH W VIL tWCH tDZC VIH Hi-Z VIL tDS
tCWL tWP
tPCS tWP
tWCH tDH
DATA VALID-1
tDZC tDS Hi-Z
tDH
DATA VALID-2
DQ (INPUTS)
tCLZ
DQ (OUTPUTS)
tCLZ Hi-Z tOEZ tODD tDZO tOEZ tODD tOEH Hi-Z
VOH Hi-Z VOL tDZO VIH
OE VIL
18
MITSUBISHI ELECTRIC
Preliminary Spec.
MITSUBISHI LSIs
MH16V72TJ -6, -7
Rev.3 '96.6.19
FAST PAGE MODE 1207959552 - BIT ( 16777216 - WORD BY 72 - BIT ) DYNAMIC RAM
Fast Page Mode Read-Write,Read-Modify-Write Cycle
tRAS VIH VIL tCSH tCRP VIH VIL tASR tRAD tRAH tASC tCAH tASC tCAH tCWL tRCD tCAS tCP CAS tPRWC tCAS
tRP
RAS
tRWL
tASR
ROW ADDRESS
VIH
A0/B0-A12
VIL
ROW ADDRESS A11
COLUMN-1
COLUMN-2
tAWD tRCS VIH VIL tRWD tDZC
DQ (INPUTS)
tAWD tCWL tWP tRCS tCWD tWP
tCWD
W
tCPWD tDS tDH
DATA VALID-1
tDZC tDS Hi-Z tCAC tAA tCLZ
tDH
DATA VALID-2
VIH Hi-Z VIL tCAC tAA tCLZ
DQ (OUTPUTS)
VOH Hi-Z VOL tRAC tDZO VIH VIL tOEA
DATA VALID-1
Hi-Z tODD tOEZ tDZO tOEA tCPA
DATA VALID-1
Hi-Z tODD tOEZ tOEH
OE
19
MITSUBISHI ELECTRIC

▲Up To Search▲

Price & Availability of 16V72TJ

	To Download 16V72TJ Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .