| PART |
Description |
Maker |
| SI9731DQ SI9731DB SI9731 |
UP Controlled Battery Charger For 1-Cell Li-ion or 1-Cell to 3-Cell NiCd/NiMH Batteries
|
VISAY[Vishay Siliconix]
|
| 3D7323H-200 3D7323H-500 3D7323Z-30 3D7323K-25 3D73 |
MONOLITHIC TRIPLE FIXED DELAY LINE ACTIVE DELAY LINE, TRUE OUTPUT, PDSO8
MONOLITHIC TRIPLE FIXED DELAY LINE ACTIVE DELAY LINE, TRUE OUTPUT, PDIP14
|
Data Delay Devices, Inc.
|
| LM2576HVT-12 LM2576HVT-15 LM2576HVS-5.0 LM2576HVS- |
regulators are monolithic integrated circuits that provide all the active functions for a step-down switching
regulators are monolithic integrated circuits that provide all the active functions for a step-down switching
|
Tiger Electronic Co.,Ltd
Tiger Electronic Co.,Lt...
|
| 3D7324G-200 3D7324G-40 3D7324D-8 3D7324G-30 3D7324 |
MONOLITHIC QUADRUPLE FIXED DELAY LINE ACTIVE DELAY LINE, TRUE OUTPUT, PDSO14
|
Data Delay Devices, Inc.
DATA DELAY DEVICES INC
|
| 3D3324G-6000 3D3324 3D3324-10 3D3324-100 3D3324-10 |
MONOLITHIC QUADRUPLE FIXED DELAY LINE ACTIVE DELAY LINE, TRUE OUTPUT, PDSO14
|
DATADELAY[Data Delay Devices, Inc.]
|
| MM1433 |
IC for Control of Lithium-ion Batteries Charging (one cell ~ two cell)
|
Mitsumi
|
| MAX17049G MAX17049GT10 MAX17048 |
Micropower 1-Cell/2-Cell Li ModelGauge ICs
|
Maxim Integrated Products
|
| MMSZ5255B MMSZ5244B |
3.08V uP Supervisory Circuit with Active High and Active Low Complementary outputs, Pb-Free Device; Package: Micro8™; No of Pins: 8; Container
5% TOLERANCE
|
Fairchild Semiconductor Corporation
FAIRCHILD[Fairchild Semiconductor]
|
| AT40K-FFT AT40K05LV AT40K20 AT40K20LV AT40K40 AT40 |
AT40K-FFT [Updated 8/98. 8 Pages] Fast fourier transform Intellectual Property Core for AT40K FPGAs
From old datasheet system
5K - 50K Gate FPGA with DSP Optimized Core Cell and Distributed FreeRam.
20K Gate FPGA with DSP Optimized Core Cell and Distributed FreeRam (5V)
20K Gate FPGA with DSP Optimized Core Cell and Distributed FreeRam (3.3V)
40K Gate FPGA with DSP Optimized Core Cell and Distributed FreeRam (5V)
10K Gate FPGA with DSP Optimized Core Cell and Distributed FreeRam (5V)
10K Gate FPGA with DSP Optimized Core Cell and Distributed FreeRam (3.3V)
5K - 50K Gate FPGA with DSP Optimized Core Cell and Distributed FreeRam (3.3V)
5K Gate FPGA with DSP Optimized Core Cell and Distributed FreeRam (5V)
|
Atmel Corp
|
| EP8319-RC EP8301 EP8301-RC EP8302 EP8302-RC EP8303 |
ACTIVE DELAY LINE, TRUE OUTPUT, PDIP14
14 Pin DIP 10 Tap TTL Compatible Active Delay Lines
|
PCA ELECTRONICS INC.
|
