| PART |
Description |
Maker |
| W9751G6KB-18 W9751G6KB-25 W9751G6KB-3 W9751G6KB25A |
Double Data Rate architecture: two data transfers per clock cycle
|
Winbond
|
| K4D263238M K4D263238M-QC45 K4D263238M-QC50 K4D2632 |
1M x 32Bit x 4 Banks Double Data Rate Synchronous RAM with Bi-directional Data Strobe and DLL
|
Samsung Electronic
SAMSUNG[Samsung semiconductor]
|
| IS61VPD102418A-250TQ IS61VPD102418A-250TQI IS61VPD |
512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM 1M X 18 CACHE SRAM, 2.6 ns, PQFP100
512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM 512K X 36 CACHE SRAM, 2.6 ns, PBGA165
|
Integrated Silicon Solution, Inc.
INTEGRATED SILICON SOLUTION INC
|
| IS61VPD25636A-200TQ2I IS61VPD51218A-200B2I |
256K x 36, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM 256K X 36 CACHE SRAM, 3.1 ns, PQFP100
256K x 36, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM 512K X 18 CACHE SRAM, 3.1 ns, PBGA119
|
Integrated Silicon Solution, Inc.
|
| DDR110-56T7RL DDR110-XXT7RL DDR110-27T7RL |
10-LINE 56 ohm OTHER TERMINATOR, PDSO24
DOUBLE DATA RATE TERMINATION NETWORK WITH DISABLE SWITCH 双倍数据速率终端网络具有禁用开
DOUBLE DATA RATE TERMINATION NETWORK WITH DISABLE SWITCH
|
STMicroelectronics N.V.
STMICROELECTRONICS[STMicroelectronics]
ST Microelectronics
|
| IS61LPD51218A-250TQI IS61VPD25636A-200B2 IS61VPD25 |
256K x 36, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM
256K x 36, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM
|
Integrated Silicon Solu...
|
| K7P801811M K7P803611M |
256Kx36 & 512Kx18 Synchronous Pipelined SRAM Data Sheet
|
Samsung Electronic
|
| CY7C1372CV25-167AI CY7C1372CV25-167BGI CY7C1372CV2 |
512K x 36/1M x 18 Pipelined SRAM with NoBLArchitecture 1M X 18 ZBT SRAM, 3 ns, PQFP100
512K x 36/1M x 18 Pipelined SRAM with NoBLArchitecture 1M X 18 ZBT SRAM, 3 ns, PBGA165
512K x 36/1M x 18 Pipelined SRAM with NoBLArchitecture 1M X 18 ZBT SRAM, 3 ns, PBGA119
512K x 36/1M x 18 Pipelined SRAM with NoBLArchitecture 1M X 18 ZBT SRAM, 2.8 ns, PBGA119
512K x 36/1M x 18 Pipelined SRAM with NoBLArchitecture 1M X 18 ZBT SRAM, 2.8 ns, PBGA165
512K x 36/1M x 18 Pipelined SRAM with NoBLArchitecture 512K X 36 ZBT SRAM, 3 ns, PBGA165
512K x 36/1M x 18 Pipelined SRAM with NoBLArchitecture 512K X 36 ZBT SRAM, 3 ns, PQFP100
512K x 36/1M x 18 Pipelined SRAM with NoBLArchitecture 512K X 36 ZBT SRAM, 3.4 ns, PQFP100
512K x 36/1M x 18 Pipelined SRAM with NoBLArchitecture 512K X 36 ZBT SRAM, 3.4 ns, PBGA165
512K x 36/1M x 18 Pipelined SRAM with NoBLArchitecture 12k × 36/1M × 18流水线的SRAM架构的总线延迟
CAP,Ceramic,10000pF,500VDC,10-% Tol,10% Tol,X7R-TC Code,-15,15%-TC,30ppm-TC RoHS Compliant: Yes
512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture
|
Cypress Semiconductor, Corp.
Cypress Semiconductor Corp.
|
| A65H83181 A65H83181P-5 A65H83181P-6 |
128K x 36 & 256K x 18 Late Write Synchronous Fast SRAM with Pipelined Data Output
|
AMIC Technology
|
