| PART |
Description |
Maker |
| CD4013BMS CD4013BE CD4013 FN3080 |
D-Type Flip Flop, Dual, Rad-Hard, CMOS, Logic
From old datasheet system
CMOS Dual ‘D’-Type Flip-Flop
CMOS Dual ??Type Flip-Flop
IC-4000CMOS
CMOS Dual D-Type Flip-Flop
CMOS Dual ‘D?Type Flip-Flop
|
INTERSIL[Intersil Corporation]
|
| 74AUP2G80GN 74AUP2G80GD |
Low-power dual D-type flip-flop; positive-edge trigger AUP/ULP/V SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, INVERTED OUTPUT, PDSO8
Low-power dual D-type flip-flop; positive-edge trigger 低功耗双D型触发器;上升沿触
|
NXP Semiconductors N.V.
|
| SN74LS377D SN74LS377N SN74LS379D SN74LS379DW SN74L |
OCTAL D FLIP-FLOP WITH ENABLE; HEX D FLIP-FLOP WITH ENABLE; 4-BIT D FLIP-FLOP WITH ENABLE LS SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP16
OCTAL D FLIP-FLOP WITH ENABLE; HEX D FLIP-FLOP WITH ENABLE; 4-BIT D FLIP-FLOP WITH ENABLE LS SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO20
OCTAL D FLIP-FLOP WITH ENABLE HEX D FLIP-FLOP WITH ENABLE 4-BIT D FLIP-FLOP WITH ENABLE
|
Motorola Mobility Holdings, Inc.
MOTOROLA[Motorola, Inc]
|
| 74LV109 74LV109D 74LV109DB 74LV109N 74LV109PW 74LV |
Dual JK flip-flop with set and reset; positive-edge trigger LV/LV-A/LVX/H SERIES, DUAL POSITIVE EDGE TRIGGERED J-KBAR FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16
From old datasheet system
|
NXP Semiconductors N.V.
PHILIPS[Philips Semiconductors]
|
| 74LV107 74LV107D 74LV107DB 74LV107N 74LV107PW 74LV |
CLP SINE LV/LV-A/LVX/H SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14
Dual JK flip-flop with reset; negative-edge trigger
|
NXP Semiconductors N.V.
PHILIPS[Philips Semiconductors]
|
| MC74HC76 MC74HC76D MC74HC76N ON1498 |
From old datasheet system
DUAL JK FLIP-FLOP WITH SER AND RESET
Dual JK Flip-Flop With Set and Reset
|
MOTOROLA[Motorola, Inc]
ON Semi
|
| MC74HC109 ON1335 |
Dual J-K Flip-Flop with Set and Rest
From old datasheet system
DUAL J-K FLIP-FLOP WITH SET AND RESET
|
Motorola, Inc
ON Semi
|
| 74LCX112SJ 74LCX112 74LCX112M 74LCX112MTC 74LCX112 |
Low Voltage Dual J-K Negative Edge-Triggered Flip-Flop with 5V Tolerant Inputs LVC/LCX/Z SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16
From old datasheet system
|
Fairchild Semiconductor, Corp.
http://
FAIRCHILD[Fairchild Semiconductor]
|
| DM74AS74 DM74AS74SJX DM74AS74M DM74AS74N DM74AS74S |
Dual D-Type Positive-Edge-Triggered Flip-Flop with Preset and Clear AS SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP14
Dual D Positive-Edge-Triggered Flip-Flop with Preset and Clear
|
Fairchild Semiconductor, Corp.
FAIRCHILD[Fairchild Semiconductor]
|
| NC7SZ175P6 NC7SZ175P6X NC7SZ175 NC7SZ175L6X |
TinyLogic UHS D-Type Flip-Flop LVC/LCX/Z SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, DSO6
TinyLogic UHS D-Type Flip-Flop
TinyLogic UHS D-Type Flip-Flop
|
Fairchild Semiconductor, Corp.
FAIRCHILD[Fairchild Semiconductor]
|
| HD74HCT74A HD74HCT74AT HD74HCT74AFP |
Dual D-type Positive Edge-triggered Flip Flops with Clear and Preset
Octal D-Type Edge Triggered Flip-Flops with 3-State Outputs 20-CDIP -55 to 125
FLIP-FLOP|DUAL|D TYPE|HCT-CMOS|TSSOP|14PIN|PLASTIC
FLIP-FLOP|DUAL|D TYPE|HCT-CMOS|SOP|14PIN|PLASTIC
|
Hitachi,Ltd.
HITACHI[Hitachi Semiconductor]
|
