| PART |
Description |
Maker |
| ISPLSI2064VL-100LB100 ISPLSI2064VL-100LJ44 ISPLSI2 |
2.5V In-System Programmable SuperFAST?High Density PLD
2.5V In-System Programmable SuperFAST?/a> High Density PLD
2.5V In-System Programmable SuperFAST⑩ High Density PLD
2.5V In-System Programmable SuperFAST High Density PLD
Turns Counting Dial; Number of Turns:10; Knob/Dial Style:Round Skirted With Indicator Line; Body Material:Aluminum; Shaft Size:1/4; Color:Satin RoHS Compliant: Yes EE PLD, 10 ns, PQFP100
2.5V In-System Programmable SuperFASTHigh Density PLD EE PLD, 10 ns, PQFP100
2.5VIn-SystemProgrammableSuperFASTHighDensityPLD
|
LATTICE[Lattice Semiconductor]
Lattice Semiconductor Corporation
Lattice Semiconductor, Corp.
|
| ISPLSI2032VL-135LT44I ISPLSI2096VL ISPLSI2096VL-10 |
2.5VIn-SystemProgrammableSuperFASTHighDensityPLD
2.5V In-System Programmable SuperFAST⑩ High Density PLD
2.5V In-System Programmable SuperFAST High Density PLD
2.5V In-System Programmable SuperFASTHigh Density PLD EE PLD, 8 ns, PQFP128
2.5V In-System Programmable SuperFASTHigh Density PLD EE PLD, 10 ns, PQFP44
|
LATTICE[Lattice Semiconductor]
LATTICE [Lattice Semiconductor]
Lattice Semiconductor Corporation
Lattice Semiconductor, Corp.
|
| ISPLSI1024 ISPLSI1024EA-200LT100 1024EA ISPLSI1024 |
200 MHz in-system prommable high density PLD
Shielded Paired Cable; Number of Conductors:8; Conductor Size AWG:28; No. Strands x Strand Size:7 x 36; Jacket Material:Polyethylene; Number of Pairs:4; Features:Alumunium Foil Polyester/Tinned Copper Braid; Impedance:120ohm RoHS Compliant: Yes
In-System Programmable High Density PLD
100 MHz in-system prommable high density PLD
|
Lattice Semiconductor Corporation
LATTICE[Lattice Semiconductor]
http://
|
| QL2009 QL2009-0PB256C QL2009-0PB256I QL2009-0PF144 |
3.3V and 5.0V pASIC 2 FPGA combining speed, density, low cost and flexibility.
3.3V and 5.0V pASIC? 2 FPGA Combining Speed Density Low Cost and Flexibility
3.3V and 5.0V pASICò 2 FPGA
3.3V and 5.0V pASIC? 2 FPGA Combining Speed, Density, Low Cost and Flexibility
3.3V and 5.0V pASIC 2 FPGA Combining Speed/ Density/ Low Cost and Flexibility
3.3V and 5.0V pASIC 2 FPGA Combining Speed, Density, Low Cost and Flexibility(高速，高可用密度，低成本、可适应性强.3V.0V pASIC 2系列场可编程逻辑器件)
PT 6C 6#20 PIN RECP
PT 8C 8#20 PIN RECP
3.3V and 5.0V pASIC 2 FPGA Combining Speed, Density, Low Cost and Flexibility 3.3V.0V帕希奇？ 2 FPGA的结合速度，密度，低成本和灵活
|
List of Unclassifed Manufacturers
ETC[ETC]
Electronic Theatre Controls, Inc.
QuickLogic Corp.
|
| HDRIGHTANGLE 781-M15-113R141 781-M15-113R001 781-M |
MALE-HIGH DENSITY
MALE-HIGH DENSITY-MACHINED CONTACTS-RIGHT ANGLE
|
List of Unclassifed Manufacturers
|
| ISPLSI2032E ISPLSI2032E-110LJ44 ISPLSI2032E-110LT4 |
In-SystemProgrammableSuperFASTHighDensityPLD
In-System Programmable SuperFASTHigh Density PLD
In-System Programmable SuperFAST High Density PLD 在系统可编程超快高密度可编程逻辑器件
|
Lattice Semiconductor Corporation
Lattice Semiconductor, Corp.
|
| ISPLSI5512VA-70LB388 ISPLSI5512VA-70LB272 ISPLSI55 |
Electrically-Erasable Complex PLD
In-System Programmable 3.3V SuperWIDEHigh Density PLD
In-System Programmable 3.3V SuperWIDE High Density PLD
In-System Programmable 3.3V SuperWIDE?High Density PLD
|
Lattice Semiconductor Corporation
|
| ATV750 ATV750-20DM ATV750-20DM_883 ATV750-20GM ATV |
THERMISTOR GLASS 250 OHM DO-35 UV PLD, 25 ns, CDIP24
THERMISTOR GLASS 1K OHM DO-35 OT PLD, 25 ns, PDIP24
THERMISTOR GLASS 10K OHM DO-35 OT PLD, 25 ns, PDIP24
THERMISTOR GLASS 30K OHM DO-35 UV PLD, 25 ns, CDIP24
High Density UV Erasable Programmable Logic Device OT PLD, 20 ns, PDIP24
High Density UV Erasable Programmable Logic Device OT PLD, 20 ns, PDSO24
High Density UV Erasable Programmable Logic Device UV PLD, 20 ns, CDIP24
High Density UV Erasable Programmable Logic Device OT PLD, 20 ns, PQCC28
High Density UV Erasable Programmable Logic Device OT PLD, 20 ns, CQCC28
High Density UV Erasable Programmable Logic Device OT PLD, 20 ns, CDIP24
High Density UV Erasable Programmable Logic Device OT PLD, 25 ns, PDIP24
|
ATMEL[ATMEL Corporation]
Atmel Corp.
Atmel, Corp.
|
| SET111411 SET111403 SET111412 SET111419 SET111404 |
High Density,High Current,3-Phase Full Wave Bridge Rectifier(????靛?400V,娓╁害55???骞冲??存??垫?45A,楂??搴?澶х?娴?涓???ㄦ尝妗ユ?娴??)
High Density,High Current,3-Phase Full Wave Bridge Rectifier(????靛?1000V,娓╁害55???骞冲??存??垫?30A,楂??搴?澶х?娴?涓???ㄦ尝妗ユ?娴??)
3 PHASE, 30 A, SILICON, BRIDGE RECTIFIER DIODE
High Density,High Current,3-Phase Full Wave Bridge Rectifier(????靛?150V,娓╁害55???骞冲??存??垫?45A,楂??搴?澶х?娴??涓???ㄦ尝妗ユ?娴??)
High Density,High Current,3-Phase Full Wave Bridge Rectifier(反向电压1000V,温度55℃时平均整流电流45A,高密大电三相全波桥整流器) 高密度，大电3 -相全波桥式整流器（反向电000V的温5℃时平均整流电流45A条，高密度，大电流，三相全波桥整流器
HIGH CURRENT, 3-PHASE FULL WAVE BRIDGE ASSEMBLY
|
Semtech, Corp.
Semtech Corporation
|
| M38230G4-XXXFP M38230G4-XXXHP M38231G4-XXXHP M3823 |
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM; Architecture: Standard Sync, Flow-through; Density: 18 Mb; Organization: 512Kb x 36; Vcc (V): 3.1 to 3.6 V
36-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V
36-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 1.7 to 1.9 V
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 2.4 to 2.6 V
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 3.1 to 3.6 V
18-Mbit (512K x 36/1M x 18) Pipelined SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 18 Mb; Organization: 1Mb x 18; Vcc (V): 3.1 to 3.6 V
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V
72-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM; Architecture: Standard Sync, Flow-through; Density: 18 Mb; Organization: 1Mb x 18; Vcc (V): 3.1 to 3.6 V
36-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 1.7 to 1.9 V
36-Mbit (1M x 36/2 M x 18/512K x 72) Flow-Through SRAM with NoBL(TM) Architecture; Architecture: NoBL, Flow-through; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V
72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 1Mb x 72; Vcc (V): 2.4 to 2.6 V
72-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 3.1 to 3.6 V
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 512Kb x 72; Vcc (V): 3.1 to 3.6 V
72-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V
Sync SRAM; Architecture: QDR-II, 2 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V
36-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V
72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 2.4 to 2.6 V
72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 2.4 to 2.6 V
72-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 1Mb x 72; Vcc (V): 3.1 to 3.6 V
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 2.4 to 2.6 V
72-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency); Architecture: QDR-II , 4 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V
72-Mbit DDR-II SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency); Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V 单芯位CMOS微机
72-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM; Architecture: Standard Sync, Flow-through; Density: 18 Mb; Organization: 1Mb x 18; Vcc (V): 3.1 to 3.6 V 单芯位CMOS微机
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 单芯位CMOS微机
72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 2.4 to 2.6 V 单芯位CMOS微机
72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 2.4 to 2.6 V 单芯位CMOS微机
72-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
72-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
36-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 单芯8位CMOS微机
Sync SRAM; Architecture: QDR-II, 2 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
36-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
72-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V
36-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V
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Renesas Electronics Corporation.
Renesas Electronics, Corp.
|
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