| PART |
Description |
Maker |
| ADLQM67PC-3517UE |
Hardware monitor with api
|
ADL Embedded Solutions
|
| OS21 |
The API defined in the OS21 User manual
|
STMicroelectronics
|
| CY7C1350F CY7C1350F-100AC CY7C1350F-100AI CY7C1350 |
4-Mb (128K x 36) Pipelined SRAM with Nobl Architecture 128K X 36 ZBT SRAM, 2.8 ns, PBGA119 4-Mb (128K x 36) Pipelined SRAM with Nobl Architecture 128K X 36 ZBT SRAM, 4.5 ns, PQFP100 4-Mb (128K x 36) Pipelined SRAM with Nobl Architecture 128K X 36 ZBT SRAM, 2.6 ns, PBGA119 4-Mb (128K x 36) Pipelined SRAM with Nobl Architecture 128K X 36 ZBT SRAM, 2.6 ns, PQFP100 CABLE ASSEMBLY; LEAD-FREE SOLDER; SMA MALE TO SMA MALE; 50 OHM, PE-SR047FL (.047" RE-SHAPABLE) 128K X 36 ZBT SRAM, 3.5 ns, PQFP100 4-Mb (128K x 36) Pipelined SRAM with Nobl Architecture 128K X 36 ZBT SRAM, 2.8 ns, PQFP100 4-Mb (128K x 36) Pipelined SRAM with Nobl(TM) Architecture
|
Cypress Semiconductor, Corp. Cypress Semiconductor Corp. CYPRESS[Cypress Semiconductor]
|
| CAT64LC20ZS CAT64LC20ZP CAT64LC20J-TE7 CAT64LC20J- |
36-Mbit QDR-II SRAM 4-Word Burst Architecture 36-Mbit QDR-II SRAM 2-Word Burst Architecture 9-Mbit (256K x 36/512K x 18) Pipelined SRAM with NoBL Architecture 4-Mbit (128K x 36) Pipelined SRAM with NoBL Architecture 4-Mbit (128K x 36) Flow-through SRAM with NoBL Architecture 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBL Architecture SPI Serial EEPROM SPI串行EEPROM 36-Mbit QDR™-II SRAM 2-Word Burst Architecture SPI串行EEPROM 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM SPI串行EEPROM 256K (32K x 8) Static RAM SPI串行EEPROM
|
Analog Devices, Inc. Electronic Theatre Controls, Inc.
|
| CY7C1418AV18-267BZC |
36-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V
|
CYPRESS SEMICONDUCTOR CORP
|
| CY7C1518KV18-300BZXC |
72-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V 4M X 18 DDR SRAM, 0.45 ns, PBGA165
|
Cypress Semiconductor, Corp.
|
| CY7C1518JV18-250BZC CY7C1518JV18-300BZXC |
72-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V 4M X 18 DDR SRAM, 0.45 ns, PBGA165
|
Cypress Semiconductor, Corp.
|
| CY7C1307AV18-167BZC CY7C1307AV18 CY7C1307AV18-100B |
18-Mb Burst of 4 Pipelined SRAM with QDR垄芒 Architecture 18-Mb Burst of 4 Pipelined SRAM with QDR Architecture
|
Cypress Semiconductor
|
| CY7C1305BV25 CY7C1305BV25-100BZC CY7C1305BV25-167B |
18-Mbit Burst of 4 Pipelined SRAM with QD(TM) Architecture 18-Mbit Burst of 4 Pipelined SRAM with QDR Architecture From old datasheet system
|
CYPRESS[Cypress Semiconductor]
|
| CY7C1474V33-250BGI CY7C1474V33-250BGXC CY7C1474V33 |
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL垄芒 Architecture 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL Architecture 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL?Architecture
|
Cypress Semiconductor
|
| CY7C1370CV CY7C1372CV25-250BZI CY7C1370CV25 CY7C13 |
512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture 512K x 36/1M x 18 Pipelined SRAM with NoBL(TM) Architecture 512K x 36/1M x 18 Pipelined SRAM with NoBL⑩ Architecture
|
CYPRESS[Cypress Semiconductor]
|
| CY7C1304DV25-167BZC CY7C1304DV25-167BZI CY7C1304DV |
9-Mbit Burst of 4 Pipelined SRAM with QDR Architecture 9-Mbit Burst of 4 Pipelined SRAM with QDR⑩ Architecture
|
Cypress Semiconductor
|