| PART |
Description |
Maker |
| ADN2818ACPZ-RL |
Continuous Rate 10 Mbps to 2.7 Gbps Clock and Data Recovery IC; Package: LFCSP (5x5mm CP-32-2); No of Pins: 32; Temperature Range: Industrial CLOCK RECOVERY CIRCUIT, QCC32
|
Analog Devices, Inc.
|
| W9725G6KB25A W9725G6KB-25 W9725G6KB-18 W9725G6KB-3 |
DLL aligns DQ and DQS transitions with clock, Data masks (DM) for write data, Write Data Mask
|
Winbond
|
| 1064101200 |
QSFP to QSFP Quad Data Rate PSM4 Active Optical Cable, 40 Gbps Data Rate
|
Molex Electronics Ltd.
|
| CY2PP3220AI CY2PP3220AIT CY2PP3220 |
Dual 1:10 Differential Clock/Data Fanout Buffer
Dual 1:10 Differential Clock / Data Fanout Buffer 2PP SERIES, LOW SKEW CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52
|
CYPRESS[Cypress Semiconductor]
Cypress Semiconductor, Corp.
|
| MAX9320EUA-T MAX9320AEKA-T |
2.25 V to 3.8 V, 1:2 differential LVPECL/LVECL/HSTL clock and data driver
1:2 Differential LVPECL/LVECL/HSTL Clock and Data Drivers 9320 SERIES, LOW SKEW CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8
|
MAXIM - Dallas Semiconductor
Maxim Integrated Products, Inc.
|
| M13L2561616A-2A |
Double-data-rate architecture, two data transfers per clock cycle
|
Elite Semiconductor Mem...
|
| W972GG6JB W972GG6JB-25 |
16M ?8 BANKS ?16 BIT DDR2 SDRAM
Double Data Rate architecture: two data transfers per clock cycle
|
Winbond
|
| ADN2905 |
CPRI and 10G Ethernet Data Recovery IC with Amp/EQ from 614.4 Mbps to 10.3125 Gbps
|
Analog Devices
|
| NBSG53A-D |
2.5V/3.3V SiGe Selectable Differential Clock and Data D Flip-Flop/Clock Divider with Reset and OLS*
|
ON Semiconductor
|
| 1064111050 |
QSFP to QSFP Fourteen Data Rate PSM4 Active Optical Cable, 56 Gbps Data Rate
|
Molex Electronics Ltd.
|
