| PART |
Description |
Maker |
| TC4027BFN |
DUAL J-K MASTER - SLAVE FLIP FLOP
|
TOSHIBA
|
| MC10H131 MC10H131FNG MC10H131FNR2G MC10H131PG MC10 |
Dual D Type Master┸Slave Flip┸Flop
|
ON Semiconductor
|
| MC1023102 MC10231P MC10231 MC10231FN MC10231L MC10 |
High Speed Dual Type D Master-Slave Flip-Flop
|
ONSEMI[ON Semiconductor]
|
| 74LS112 DM74LS112A DM74LS112AN DM74KS112AM |
From old datasheet system
Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs
Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset/ Clear/ and Complementary Outputs
|
FAIRCHILD[Fairchild Semiconductor]
|
| CD4027BC |
Dual J-K Master/Slave Flip-Flop with Set and Reset
From old datasheet system
|
Fairchild
|
| HCF4096M013TR |
GATE J-K MASTER-SLAVE FLIP-FLOPS
|
ST Microelectronics
|
| CD4096B |
Inverting Gated JK Master Slave Flip Flop
|
ETC
|
| MC10H135FN MC10H13506 MC10H135FNG MC10H135FNR2 MC1 |
Dual J−K Master−Slave Flip−Flop
|
ONSEMI[ON Semiconductor]
Rectron Semiconductor
|
| 7476 |
Dual Master Slave J-K F-F
|
Fairchild Semiconductor
|
| MC10H109FNR2 MC10H131 MC100EP140 MC100E155FN MC100 |
Dual 4-5-Input OR/NOR Gate
Dual Type D Master-Slave Flip-Flop
3.3V ECL Phase-Frequency Detector
5V ECL 6-Bit 2:1 Mux Latch
5V ECL Differential Data and Clock D Flip-Flop
3.3 V 1:9 Differential HSTL/PECL to HSTL Clock Driver with LVTTL Clock Select and Enable
3.3V ECL 1:15 Differential ÷1/÷2 Clock Driver
ECL/TTL Clock Driver
3.3V / 5V 2-Input Differential AND/NAND
5V ECL 2:1 Multiplexer
3.3V / 5V ECL JK Flip Flop
3.3V ECL 1:4 ÷ 1/÷ 2 Clock Fanout Buffer
3.3V / 5V Hex Differential Line Receiver / Driver
3.3V 10-bit LVTTL/LVCMOS to LVPECL Translator
Dual 2-Bit Adder/Subtractor
|
ON Semiconductor
|
| MC10135 MC10135FN MC10135L MC10135P ON0571 |
Replaced by SN54LS175 : Quadruple D-type Flip-Flops With Clear 16-CFP -55 to 125 10K SERIES, POSITIVE EDGE TRIGGERED JBAR-KBAR FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP16
Replaced by SN54LS175 : Quadruple D-type Flip-Flops With Clear 16-CDIP -55 to 125 10K SERIES, POSITIVE EDGE TRIGGERED JBAR-KBAR FLIP-FLOP, COMPLEMENTARY OUTPUT, CDIP16
Dual J-K Master-Slave Flip-Flop
PIN ASSIGNMENT
From old datasheet system
|
Motorola Mobility Holdings, Inc.
Motorola, Inc.
ONSEMI[ON Semiconductor]
|
