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Cypress
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| Part No. |
CY7C1317BV18
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| OCR Text |
... peripheral circuitry and a two-bit burst counter. addresses for read and write are latched on alternate rising edges of the input (k) clock...1m x 18 array clk a (19:0) gen. k k control logic address register read add. decode read data reg. r... |
| Description |
18-Mbit DDR-II SRAM 4-Word Burst Architecture
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| File Size |
307.89K /
24 Page |
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Cypress Semiconductor Corp.
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| Part No. |
CY7C1429AV18 CY7C1422AV18
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| OCR Text |
...cation is associated with two 8-bit words in the case of cy7c1422av18, two 9-bit words in the case of cy7c1429av18, two 18-bit words in the ...1m x 18 clk a (19:0) gen. k k control logic address register d [17:0] read add. decode read data reg... |
| Description |
36-Mbit DDR-II SIO SRAM 2-Word Burst Architecture(2字Burst结构36-Mbit DDR-II SIO SRAM) 36兆位的DDR - II二氧化硅的SRAM 2字突发架构（2字突发结36 -兆位的DDR - II二氧化硅的SRAM
36-Mbit DDR-II SIO SRAM 2-Word Burst Architecture(2字Burst结构6-Mbit DDR-II SIO SRAM) 36兆位的DDR - II二氧化硅的SRAM 2字突发架构（2字突发结36 -兆位的DDR - II二氧化硅的SRAM
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| File Size |
418.42K /
28 Page |
View
it Online |
Download Datasheet |
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