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Integrated Device Technology, Inc.
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| Part No. |
IDTCSPUA877ABVG
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| OCR Text |
...ble in 52-ball vfbga and 40-pin vfqfpn packages functional block diagram note: the logic detect (ld) powers down the device when a logic low...32, 35, 37, 40 buffered output of input clock, clk n b no ball
5 idtcspua877a 1.8v pll differen... |
| Description |
1.8V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
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| File Size |
118.17K /
14 Page |
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it Online |
Download Datasheet
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IDT
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| Part No. |
CSPU877NL8 CSPU877BV8 CSPU877BVG CSPU877BVG8
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| OCR Text |
...ble in 52-ball vfbga and 40-pin vfqfpn packages applications: ? meets or exceeds jedec standard 82-8 for registered ddr2 clock driver ? alon...32, 35, 37, 40 buffered output of input clock, clk
5 idtcspu877 1.8v pll differential 1:10 sdram... |
| Description |
1.8V PLL Differential 1:10 SDRAM Clock Driver
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| File Size |
137.53K /
13 Page |
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it Online |
Download Datasheet |
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IDT
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| Part No. |
IDT5T93GL16NLI8
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| OCR Text |
...mode ? 2.5v v dd ? available in vfqfpn package applications: ? clock distribution functional block diagram
industrial temperature range 2 ...32 31 29 28 27 v dd g 2 a 2 q 12 q 12 q 11 q 11 q 10 q 10 q 9 q 9 v dd a 2 23 24 19 14 15 16 17 18 2... |
| Description |
2.5V LVDS 1:16 Glitchless Clock Buffer TeraBuffer II
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| File Size |
116.64K /
15 Page |
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it Online |
Download Datasheet |
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IDT
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| Part No. |
IDT5T93GL10NLI8
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| OCR Text |
...mode ? 2.5v v dd ? available in vfqfpn package applications: ? clock distribution functional block diagram
industrial temperature range 2 ...32 31 40 v d d s e l q 1 0 q 1 0 q 9 q 9 q 8 q 8 v d d f s e l 1 2 3 4 5 6 7 8 9 10 v dd g 1 q 1 q 1... |
| Description |
2.5V LVDS 1:10 Glitchless Clock Buffer TeraBuffer II
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| File Size |
111.54K /
15 Page |
View
it Online |
Download Datasheet |
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Price and Availability
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