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| Part No. |
HDMP-2689
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| OCR Text |
...t and serialized at 1.0625 gbd (half rate) or 2.125 gbd (full rate). the high-speed outputs can be figure 2. tx and rx paths. interfaced di...control clock generator decode 8b/10b encode 8b/10b de-serializer loopback control input latch bit r... |
| Description |
Quad 2.125/1.0625 GBd Fibre Channel General Purpose SerDes
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| File Size |
350.67K /
28 Page |
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it Online |
Download Datasheet
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| Part No. |
HMC848LC5
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| OCR Text |
... and falling edges of the half-rate clock to sample the input data in sequence, d0-d3 and latches the data onto the differenti...control pin, vctrl, which allows for loss compensation or signal level optimization. the hmc848lc5... |
| Description |
45 Gbps, 1:4 DEMUX WITH PROGRAMMABLE OUTPUT VOLTAGE
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| File Size |
799.17K /
10 Page |
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it Online |
Download Datasheet
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