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Siliver
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| Part No. |
AG1170
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| OCR Text |
...n at the required frequency and cadence. The toggling of the F/R pin produces a balanced signal at Tip and Ring. These signal waveforms are shown in Figure 4. Ringing voltage of approximately 65Vrms is applied to a single handset. It is imp... |
| Description |
Low Power Ringing SLIC
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| File Size |
378.73K /
15 Page |
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it Online |
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Silver
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| Part No. |
AG1160
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| OCR Text |
...n at the required frequency and cadence. The toggling of the F/R pin produces a balanced signal at Tip and Ring. These signal waveforms are shown in Figure 3. During ringing the integral DC-DC converter automatically switches to produce a b... |
| Description |
RINGING SLIC
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| File Size |
176.49K /
12 Page |
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it Online |
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Atmel
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| Part No. |
ATL35
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| OCR Text |
...esign Systems Supported
System cadence Design Systems, Inc.
(R)
Tools Opus - Schematic and Layout NC VerilogTM - Verilog Simulator PearlTM - Static Path Verilog-XLTM - Verilog Simulator BuildGatesTM - Synthesis (Ambit) ModelSim(R) - Ve... |
| Description |
The ATL35 series ASIC family is fabricated on a 0.35 micron CMOS process with up to four levels of metal. This family features arrays with up to 2.7 million routable gates and 976 pins. The high density and high pin count capabilities of t
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| File Size |
268.46K /
21 Page |
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it Online |
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CONSUMER MICROCIRCUITS LIMITED
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| Part No. |
CMX868
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| OCR Text |
...re Answer tone recognition. The cadence is 0.6s ON, 1.75s OFF (typ.). For V.22bis and V.22 this tone is NOT permitted, but details are included below for other applications: TX Mode ($E1) b15...b12 = 0001 (select DTMF / Tones) b3...b0 = 100... |
| Description |
V.22bis Call Setup with the CMX868
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| File Size |
48.16K /
9 Page |
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it Online |
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Altera Corporation
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| Part No. |
ACEX1K03 EP1K30TC144-3N EP1K10TC144-3N EP1K100FC256-3 EP1K100FI484-2 EP1K100QC208-3 EP1K30FC256-3 EP1K50QC208-3 EP1K50QC208-3N EP1K10TC144-1 EP1K50TC144-3N EP1K10TC144-2N
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| OCR Text |
...ools from manufacturers such as cadence, Exemplar Logic, Mentor Graphics, OrCAD, Synopsys, Synplicity, VeriBest, and Viewlogic Notes (1), (2) 208-Pin PQFP
120 147 147 147
Table 2. ACEX 1K Package Options & I/O Pin Count Device
EP1K10 E... |
| Description |
LOADABLE PLD, 0.4 ns, PQFP144
ACEX 1K Programmable Logic Device Family
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| File Size |
532.59K /
86 Page |
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it Online |
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Price and Availability
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