| |
|
 |
Integrated Device Techn...
|
| Part No. |
82P33810
|
| OCR Text |
...and apll2 generate clocks with jitter < 1 ps rms (12 khz to 20 mhz) for: 1000base-t and 1000base-x ? fractional-n input dividers suppor t a...attenuating analog plls (apll s). the output clocks generated by apll1 and apll2 are suitabl e for s... |
| Description |
Composite clock inputs
|
| File Size |
224.09K /
13 Page |
 View
it Online |
Download Datasheet
|
| |
|
|
Integrated Device Techn...
|
| Part No. |
82P33814
|
| OCR Text |
...and apll2 generate clocks with jitter < 1 ps rms (12 khz to 20 mhz) for: 1000base-t and 1000base-x ? fractional-n input dividers suppor t a...attenuating analog plls (apll s). the output clocks generated by apll1 and apll2 are suitabl e for s... |
| Description |
Differential reference inputs
|
| File Size |
232.84K /
13 Page |
View
it Online |
Download Datasheet |
| |
|
|
Integrated Device Techn...
|
| Part No. |
82P33831
|
| OCR Text |
...based and generates clocks with jitter <0.3 ps rms (10 khz to 20 mhz) for: 10gbase-r, 10gbase-w and 40gbase-r ? apll1 and apll2 generate cl...attenuating analog plls (apll s). the output clocks generated by apll1 and apll2 are suitabl e for s... |
| Description |
Composite clock inputs
|
| File Size |
222.51K /
13 Page |
View
it Online |
Download Datasheet |
| |
|
|
Integrated Device Techn...
|
| Part No. |
82P33724
|
| OCR Text |
... and apll2 generate clocks with jitter < 1 ps rms (12 khz to 20 mhz) for: 1000base-t and 1000base-x ports and to generate ieee 1588 time sta...attenuating analog plls (apl ls). the output clocks generated by apll1 and apll2 are suitable for se... |
| Description |
Port Synchronizer for IEEE 1588 and Synchronous Ethernet
|
| File Size |
232.45K /
13 Page |
View
it Online |
Download Datasheet |
| |
|
|
Integrated Device Techn...
|
| Part No. |
82P33810ABAG8
|
| OCR Text |
...and apll2 generate clocks with jitter < 1 ps rms (12 khz to 20 mhz) for: 1000base-t and 1000base-x ? fractional-n input dividers suppor t a...attenuating analog plls (apll s). the output clocks generated by apll1 and apll2 are suitabl e for s... |
| Description |
Synchronization Management Unit for IEEE 1588 and Synchronous Ethernet
|
| File Size |
279.59K /
13 Page |
View
it Online |
Download Datasheet |
| |
|
|
PMC-Sierra Inc
|
| Part No. |
PM4541
|
| OCR Text |
...rips (i.e. when configured as a jitter attenuating format converter or "CSU"). All internal registers are individually accessible and each device has been set up with individual receiver, transmitter and backplane access through headers and... |
| Description |
T1XC EVALUATION DAUGHTER BOARD
|
| File Size |
565.45K /
46 Page |
View
it Online |
Download Datasheet |
|
For
jitter-attenuating Found Datasheets File :: 73 Search Time::1.484ms
Page :: | 1 | 2 | 3 | 4 | 5 | 6 | <7> | 8 | |
▲Up To
Search▲ |
|
Price and Availability
|
