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CYPRESS
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| Part No. |
CY7C0852V
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| OCR Text |
...ess Decode
Address Decode
INTL
Interrupt Logic
MRST
Reset Logic
JTAG
TDO
Interrupt Logic
INTR
Note: 1. CY7C0851V has 16 address bits instead of 17. CY7C0832V has 18 address bits instead of 17. CY7C083XV does no... |
| Description |
3.3V 64K/128K X 36 And 128K/256K X 18 Synchronous Dual-port RAM
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| File Size |
888.72K /
32 Page |
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it Online |
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Cypress
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| Part No. |
CY7C138 7C138
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| OCR Text |
...RATION
CE R OER R/WR
SEML INTL[2] M/S
SEMR INTR[2]
C138-1
Notes: 1. BUSY is an output in master mode and an input in slave mode. 2. Interrupt: push-pull output and requires no pull-up resistor.
Cypress Semiconductor Corpor... |
| Description |
4K x 8/9 Dual-Port Static RAM From old datasheet system
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| File Size |
276.28K /
15 Page |
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it Online |
Download Datasheet
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Cypress
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| Part No. |
CY7C027V CY7C028V CY7C038V 7C038V
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| OCR Text |
...R OE R R/WR SEM R
[5]
BUSYL INTL UBL LBL
Notes: 1. Call for availability. 2. I/O8-I/O15 for x16 devices; I/O9-I/O17 for x18 devices. 3. I/O0-I/O7 for x16 devices; I/O0-I/O8 for x18 devices.
M/S
4. 5.
BUSY R INT R UBR LB R
A0-A1... |
| Description |
3.3V 32K/64K x 16/18Dual-Port Static RAM From old datasheet system
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| File Size |
332.98K /
17 Page |
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it Online |
Download Datasheet
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Cypress
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| Part No. |
CY7C027 CY7C028 CY7C038 7C038
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| OCR Text |
...14/15L CEL OEL R/WL SEM L BUSYL INTL UBL LBL
[5]
Interrupt Semaphore Arbitration
A0R-A 14/15R CER OE R R/WR SEM R
[5]
M/S
4. 5.
BUSY R INT R UBR LB R
A0-A14 for 32K; A0-A15 for 64K devices. BUSY is an output in master mode a... |
| Description |
32K/64K x 16/18Dual-Port Static RAM From old datasheet system
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| File Size |
338.13K /
18 Page |
View
it Online |
Download Datasheet
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Price and Availability
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