| |
|
 |
Ramtron
|
| Part No. |
FM25L256B
|
| OCR Text |
...enters low-power standby mode, ignores other inputs, and all outputs are tri-stated. when low, the device internally activates the sck signal. a falling edge on /cs must occur prior to every op-code. sck input serial clock: all i/o a... |
| Description |
3V F-RAM Memory
|
| File Size |
243.05K /
14 Page |
 View
it Online |
Download Datasheet
|
| |
|
|
Cypress Semiconductor, Corp.
|
| Part No. |
CY7C1548V18-300BZC CY7C1548V18-300BZI CY7C1548V18-300BZXI CY7C1548V18-300BZXC CY7C1546V18-300BZI CY7C1546V18-300BZXI CY7C1548V18-375BZC CY7C1548V18-375BZI
|
| OCR Text |
...electing a nibble write select ignores the corresponding nibble of data and does not write into the device. bws 0 , bws 1 , bws 2 , bws 3 input synchronous byte write select 0, 1, 2, and 3 ? active low . sampled on the rising edge of t... |
| Description |
72-Mbit DDR-II SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) 4M X 18 DDR SRAM, 0.45 ns, PBGA165
72-Mbit DDR-II SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) 8M X 8 DDR SRAM, 0.45 ns, PBGA165
|
| File Size |
453.01K /
28 Page |
View
it Online |
Download Datasheet |
| |
|
|
Cypress Semiconductor, Corp.
CYPRESS SEMICONDUCTOR CORP
|
| Part No. |
CY7C1168V18-400BZXC CY7C1168V18-375BZXC CY7C1168V18-375BZC CY7C1166V18-400BZXC
|
| OCR Text |
...electing a nibble write select ignores the corresponding nibble of data and not written into the device. bws 0 , bws 1 , bws 2 , bws 3 input- synchronous byte write select 0, 1, 2, and 3 ? active low . sampled on the rising edge of the... |
| Description |
1M X 18 DDR SRAM, 0.45 ns, PBGA165 13 X 15 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, FBGA-165
18-Mbit DDR-II SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency) 1M X 18 DDR SRAM, 0.45 ns, PBGA165
2M X 8 DDR SRAM, 0.45 ns, PBGA165
|
| File Size |
455.35K /
27 Page |
View
it Online |
Download Datasheet |
| |
|
|
Ramtron
|
| Part No. |
FM25040C
|
| OCR Text |
...s low - power standby mode , ignores other inputs, and all outputs are tri - stated. when low, the device internally activates the sck signal. a falling edge on /cs must occur prior to every op - code. sck input seria... |
| Description |
4Kb Serial 5V F-RAM Memory
|
| File Size |
331.92K /
13 Page |
View
it Online |
Download Datasheet |
| |
|
|
Ramtron
|
| Part No. |
FM25L512
|
| OCR Text |
...enters low-power standby mode, ignores other inputs, and all outputs are tri-stated. when low, the device internally activates the sck signal. a falling edge on /cs must occur prior to every op-code. sck input serial clock: all i/o a... |
| Description |
3V F-RAM Memory
|
| File Size |
232.68K /
13 Page |
View
it Online |
Download Datasheet |
| |
|
|
http://
|
| Part No. |
MK50H28DIP MK50H28PLCC52
|
| OCR Text |
...s only as a bus master. mk50h28 ignores the bm lines when it is a bus slave. byte selection is done as outlined in the following table. bm1 bm0 type of transfer low low entire word low high upper byte (dal<15:08>) high low lower byte (dal<0... |
| Description |
MULTI LOGICAL LINK FRAME RELAY CONTROLLER
|
| File Size |
438.63K /
64 Page |
View
it Online |
Download Datasheet |
|
Price and Availability
|
