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ICS
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| Part No. |
ICS951104
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| OCR Text |
... all PCI CLKs at logic 0 level, w hen input low besides t he PCI CLK_F clocks w hich ar e cont r ollable by I 2C bit s w het her t hey ar e ...agp or DDR clocks at logic "0" level when driven low. These stops are configurable via IIC. "Complem... |
| Description |
Programmable Timing Control Hub for P4 (P)
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| File Size |
214.63K /
19 Page |
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it Online |
Download Datasheet
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ICS
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| Part No. |
ICS94258
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| OCR Text |
.... The latency of the power down w ill not be greater than 3ms. (See M ODE table for further information.) PCI clock output. This pin is acti...agp (MHz) 66.66 66.66 66.66 66.66 66.66 66.66 66.66 66.66 66.66 66.66 66.66 66.66 66.66 66.66 66.66 ... |
| Description |
Single Chip, System Clock for PIII/1651 Chipset; SDRAM Clocks with I2C Programmability with Early PCI Clock
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| File Size |
343.99K /
20 Page |
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it Online |
Download Datasheet
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