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Integrated Device Techn...
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| Part No. |
9DBU0731AKILF 9DBU0731AKILFT
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| OCR Text |
...ed inputs and start up on first high assertion. low enters power down mode, subsequent high assertions exit power down mode. this pin has internal 120kohm pull-up resistor. 41 epad gnd connect paddle to gr ound.
7-output 1.5v pcie gen1... |
| Description |
7-Output 1.5V PCIe Gen1-2-3 Fanout Buffer
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| File Size |
208.53K /
17 Page |
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it Online |
Download Datasheet
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Integrated Circuit Syst... Integrated Device Techn...
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| Part No. |
9DBU0641
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| OCR Text |
...ed in trilevel input to select high bw, bypass or low bw mode. see pll operating mode table for details. 3 fb_dnc dnc true clock of diffe...pwr 1.5v power for differential input clock (receiver). this vdd should be treated as an analog po... |
| Description |
slew rate for each output HCSL-compatible differential input
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| File Size |
226.91K /
17 Page |
View
it Online |
Download Datasheet
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