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gen1 gen2 Datasheet PDF File

For gen1 gen2 Found Datasheets File :: 85 Search Time::0.891ms
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				Discera
Part No.	DSC557-03
OCR Text	...crystal - less two output pcie gen1/2/3 clock generator dsc 557 - 03 general description the dsc 557 - 03 is a crystal - less , two output pci express clock generator meeting gen1, gen2, and gen3 specifications . th...
Description	Crystal-less Two Output PCIe gen1/2/3 Clock Generator
File Size	564.10K / 9 Page	View it Online	Download Datasheet

				Integrated Device Technology
Part No.	9DB423BFLF 9DB423BGLFT 9DB423BFLFT
OCR Text	...skew <50ps phase jitter: pcie gen1 < 86ps peak to peak phase jitter: pcie gen2 < 3.0/3.1ps rms phase jitter: qpi < 0.5ps rms rohs compliant packaging features/benefits spread spectrum modulation tolerant, 0 to -0.5% down spread an...
Description	Four Output Differential Buffer for PCIe Gen 1, Gen 2 and QPI
File Size	281.61K / 19 Page	View it Online	Download Datasheet

				Exar Corporation
Part No.	XRS10L620 XRS10L620CV-F XRS10L620CVF
OCR Text	...OST mode. They comply with SATA gen1 specification (gen1 supports 1.5Gbps data rate) and gen2 (3Gbps data rate) specification. As for the IDE channel, the maximum transfer rate range from 16.7 MB/s to 150 MB/s. Further more, data transfer c...
Description	PCI-X to 2-SATA/1-PATA Host Controller
File Size	581.76K / 49 Page	View it Online	Download Datasheet

				Integrated Device Technology Integrated Circuit Syst...
Part No.	9DB1233 9DB1233AGLFT
OCR Text	...rds compatible to pcie gen2 and gen1. the 9db1233 is dr iv en b y a diff erential src output pair from an idt 932s421 or 932sq420 or equivalent maincloc k gener ator . it atten uates jitter on the input cloc k and has a selectable pll ba...
Description	Twelve Output Differential Buffer for PCIe Gen3 SMBus Interface/unused outputs can be disabled
File Size	183.95K / 15 Page	View it Online	Download Datasheet

				Integrated Device Technology
Part No.	ICS9ERS3165 9ERS3165BKILF 9ERS3165BGILF 9ERS3165BGILFT 9ERS3165BKILFT
OCR Text	...s. muxed src outputs meet pciex gen1 specification, except src1. ? meets pciex <85ps cycle-tocycle jitter for src[11:1] ? single-ended programmable slew rate control for rfireduction pci0/cr#_a 1 64 sclk vddpci 2 63 sdata pci1/cr#_b 3 62 re...
Description	Embedded 64-Pin Industrial Temperature Range CK505 Compatible Clock
File Size	426.11K / 27 Page	View it Online	Download Datasheet

				Integrated Device Technology
Part No.	89HP0504PB
OCR Text	...he device is optimized for pcie gen1 and gen2 high speed serial data streams and contains four data channels, each able to process 5gbps transmission rates. each channel consists of an input equalizer and amplifier, signal detection w...
Description	4 Channel 5Gbps PCIe? Signal Repeater
File Size	395.15K / 26 Page	View it Online	Download Datasheet

				Integrated Device Technology
Part No.	9DB106BFILF 9DB106BFILFT 9DB106BFLF 9DB106BGILFT 9DB106BGLF 9DB106BFLFT 9DB106BGLFT
OCR Text	...zero-delay buffer supports pcie gen1 and gen2 cloc king requirements . the 9db106 is dr iv en b y a diff erential src output pair from an idt ck410/ck505-compliant main clockgener ator . it atten uates jitter on the input cloc k and has...
Description	Six Output Differential Buffer for PCIe Gen 2
File Size	190.40K / 14 Page	View it Online	Download Datasheet

				Silicon Tech
Part No.	STE12PS
OCR Text	...n FSRPn RMONF RMONS RREF CLK_gen1 CLK_gen2 MCLK CLK_GEN3 ACin ACout O O O I I I O I I O 5/44 www.DataSheet4U.com Pin description STE12PS Table 2. Digital pins description I/O Function Pin name Reset RESETN Statu...
Description	12-Channel Integrated PSE Line Manager
File Size	474.46K / 44 Page	View it Online	Download Datasheet

				Xilinx, Inc
Part No.	XC6VLX240T-1FFG1156C XC6VLX7511
OCR Text	...press base specification 2.0 ? gen1 (2.5 gb/s) and gen2 (5 gb/s) support with gtx transceivers ? endpoint and root port capable ? x1, x2, x4, or x8 lane support per block ? gtx transceivers: up to 6.6 gb/s ? data rates below 480 mb/s supp...
Description	Virtex-6 Family Overview
File Size	301.28K / 11 Page	View it Online	Download Datasheet

				Integrated Device Technology
Part No.	ICS9DB803DI ICS9DB803DFILFT ICS9DB803DGILFT
OCR Text	...ypass mode phase jitter: pcie gen1 < 86ps peak to peak phase jitter: pcie gen2 < 3.1ps rms 48-pin ssop/tssop package available in rohs compliant packaging features/benefits spread spectrum modulation tolerant, 0 to -0.5% down spre...
Description	Eight Output Differential Buffer for PCIe Gen 2
File Size	250.48K / 21 Page	View it Online	Download Datasheet

For gen1 gen2 Found Datasheets File :: 85 Search Time::0.891ms
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