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Atmel corp
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| Part No. |
AT43USB351MNBSP AT43USB351M
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| OCR Text |
...on has one control endpoint and four additional programmable endpoints, each with their own FIFOs. Two of the endpoints have a 64-byte FIFO ...five different addressing modes supported in the AVR architecture. The memory spaces in the AVR arch... |
| Description |
Full-speed/low speed USB Microcontroller with ADC and PWM.
From old datasheet system
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| File Size |
88.51K /
10 Page |
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ramtron
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| Part No. |
AT43USB351M
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| OCR Text |
...on has one control endpoint and four additional programmable endpoints, each with their own FIFOs. Two of the endpoints have a 64-byte FIFO ...five different addressing modes supported in the AVR architecture. The memory spaces in the AVR arch... |
| Description |
Full-speed/
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| File Size |
89.95K /
10 Page |
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Xilinx
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| Part No. |
XC2S400E6FXXX
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| OCR Text |
...n
This document includes all four modules of the SpartanTM-IIE FPGA data sheet.
Module 1: Introduction and Ordering Information
DS077...five major configurable elements: * * * * * IOBs provide the interface between the package pins and ... |
| Description |
Spartan-IIE 1.8V FPGA Family
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| File Size |
780.94K /
103 Page |
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it Online |
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Intel
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| Part No. |
82091AA
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| OCR Text |
...3 3 Internal PLL APPENDIX A FDC four DRIVE SUPPORT A 1 Floppy Disk Controller Interface Signals A 2 DOR Digital Output Register A 3 TDR Enha...five interface protocols Note that the 82091AA hardware operations are the same for Compatibility an... |
| Description |
ADVANCED INTEGRATED PERIPHERAL (AIP)
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| File Size |
1,761.87K /
205 Page |
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Cypress
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| Part No. |
W40C06A 40C06A
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| OCR Text |
..., there is a maximum latency of four clock cycles, assuming the crystal oscillator is active. Clock Transmission Lines in System Applications With the increase in system clock frequencies, transmission line theory is commonly being applied ... |
| Description |
Six Outputs
From old datasheet system
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| File Size |
108.19K /
6 Page |
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it Online |
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TI
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| Part No. |
SN65LV1224BDB
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| OCR Text |
...to lock until it finds a unique four consecutive cycles of data boundary (stop/start bits) at the same position. The deserializer stays in lock until it cannot detect the same data boundary (stop/start bits) for four consecutive cycles. The... |
| Description |
1:10 LVDS Serdes Receiver 100 - 660Mbps
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| File Size |
331.81K /
24 Page |
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it Online |
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