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Silicon Storage Technology
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| Part No. |
29SF020
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| OCR Text |
... the nonvolatile write is asyn- chronous with the system; theref ore, either a data# poll- ing or toggle bit read may be simultaneous with the completion of the write cycle. if this occurs, the system may possibly get an erroneous result, i... |
| Description |
Search --To SST29SF020
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| File Size |
434.58K /
25 Page |
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it Online |
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AMCC
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| Part No. |
S4806CBI
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| OCR Text |
... system interface into the syn- chronous payload envelope (sonet/sdh tributaries) or ds3 frames (ds3 over sts-1/au-3 mode). in this mode, the atm and hdlc processors are by-passed and other protocols like ethernet can be mapped into sone... |
| Description |
STS-48/STM-16 SONET/SDH Framer and ATM/POS Mapper
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| File Size |
83.40K /
4 Page |
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it Online |
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Infineon
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| Part No. |
V23816-N1018-C23
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| OCR Text |
... also outputs a 155.52 mhz syn- chronous clock. the received data is updated on the falling edge of the positive receive clock (rxqi55p). the rx alarm (flag) indicator will switch active low if there is a loss of optical input signal (los... |
| Description |
SM 2.5 GBd SONET/SDH Transceiver
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| File Size |
259.09K /
6 Page |
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it Online |
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Maxim Integrated Products, Inc.
MAXIM - Dallas Semiconductor
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| Part No. |
MAX8620YETD MAX8620Y
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| OCR Text |
...ernal components. internal syn- chronous rectification improves efficiency and elimi- nates the external schottky diode that is required in conventional step-down converters. the output voltage is adjustable from 0.6v to 3.3v, with guarante... |
| Description |
PMIC for Microprocessors or DSPs in Portable Equipment
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| File Size |
404.82K /
18 Page |
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it Online |
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Atmel
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| Part No. |
ATMEGA64 ATMEGA64L
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| OCR Text |
.... in power-save mode, the asyn- chronous timer continues to run, allowing the user to maintain a timer base while the rest of the device is sleeping. the adc noise reduction mode stops the cpu and all i/o modules except asynchronous timer a... |
| Description |
64-Kbyte self-programming Flash Program Memory, 4-Kbyte SRAM, 2-Kbyte EEPROM, 8 Channel 10-bit A/D-converter. JTAG interface for on-chip-debug. Up to 16 MIPS throughput at 16 Mhz.
64-Kbyte self-programming Flash Program Memory, 4-Kbyte SRAM, 2-Kbyte EEPROM, 8 Channel 10-bit A/D-converter. JTAG interface for on-chip-debug. Up to 8 MIPS throughput at 8 Mhz. 3 Volt Operation.
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| File Size |
181.28K /
21 Page |
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it Online |
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Xilinx, Inc.
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| Part No. |
XCR5128-7TQ128C XCR5128-7TQ128I XCR5128-7VQ100I XCR5128-7VQ100C XCR5128-7PQ160C XCR5128-12PC84I XCR5128-10TQ128I XCR5128-12TQ128C XCR5128-15PC84I XCR5128-10PQ100C
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...3) can either be used as a syn- chronous clock (driven by an external source) or as an asynchronous clock (driven by a macrocell equation). the timing for asynchronous clocks is different in that the t co time is extended by the amount of t... |
| Description |
128 Macrocell CPLD EE PLD, 9.5 ns, PQFP160
128 Macrocell CPLD EE PLD, 9.5 ns, PQFP100
128 Macrocell CPLD 128个宏单元CPLD
128 Macrocell CPLD EE PLD, 12 ns, PQFP128
128 Macrocell CPLD EE PLD, 14.5 ns, PQFP128
128 Macrocell CPLD EE PLD, 17.5 ns, PQCC84
128 Macrocell CPLD EE PLD, 12 ns, PQFP100
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| File Size |
123.21K /
20 Page |
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it Online |
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Samsung Electronic
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| Part No. |
K7M801825M
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| OCR Text |
...m801825m are 9,437,184-bit syn- chronous static srams. the n t ram tm , or no turnaround random access memory uti- lizes all bandwidth in any combination of operating cycles. address, data inputs, and all control signals except output enabl... |
| Description |
256Kx36 & 512Kx18 Flow-Through NtRAMData Sheet
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| File Size |
383.53K /
17 Page |
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it Online |
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