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For gen-ii Found Datasheets File :: 1128 Search Time::2.906ms
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				Cypress Semiconductor
Part No.	CY7C1917KV18 CY7C1321KV18-250BZC CY7C1321KV18-250BZXC CY7C1321KV18-333BZC CY7C1317KV18 CY7C1319KV18
OCR Text	... 512 K x 8 Array 8 CLK Gen. Output Logic Control R/W C C 8 CQ CQ 8 DQ[7:0] Read Data Reg. 32 16 Control Logic 16 Reg. Reg....II SRAM ........................... 21 Power Up Sequence ..............................................
Description	18-Mbit DDR II SRAM Four-Word Burst Architecture
File Size	452.35K / 33 Page	View it Online	Download Datasheet

				Cypress Semiconductor
Part No.	CY7C1313BV18-278BZC CY7C1311BV18-278BZC CY7C1315BV18-278BZC CY7C1313BV18-167BZC CY7C1313BV18-167BZI CY7C1313BV18-200BZC CY7C1313BV18-200BZI CY7C1313BV18-200BZXC CY7C1313BV18-167BZXC CY7C1313BV18-167BZXI CY7C1313BV18-200BZXI CY7C1311BV18-250BZC CY7C1315BV18-200BZI CY7C1311BV18-200BZI CY7C1311BV18-300BZC CY7C1311BV18-250BZXC CY7C1313BV18-250BZXC CY7C1315BV18-250BZXC CY7C1313BV18-250BZC CY7C1315BV18-200BZC CY7C1311BV18-200BZC CY7C1311BV18-278BZXI CY7C1315BV18-278BZXI CY7C1313BV18-278BZXI CY7C1315BV18-167BZC CY7C1311BV18-167BZC CY7C1315BV18-167BZXC CY7C1311BV18-167BZXC
OCR Text	... 512K x 8 Array K K CLK Gen. Control Logic RPS C C DOFF Read Data Reg. 32 Control Logic 16 Reg. 16 Reg. 8 Reg. CQ CQ ...II. In the single clock mode, CQ is generated with respect to K. The timings for the echo clocks are...
Description	18-Mbit QDR?II SRAM 4-Word Burst Architecture
File Size	511.26K / 28 Page	View it Online	Download Datasheet

				Cypress Semiconductor
Part No.	CY7C1276V18-375BZC CY7C1276V18-333BZC CY7C1276V18-375BZI CY7C1276V18-300BZI CY7C1276V18-333BZXI CY7C1276V18-300BZC CY7C1276V18-300BZXI CY7C1276V18-300BZXC CY7C1276V18-333BZXC CY7C1276V18-333BZI CY7C1263V18 CY7C1263V18-300BZC CY7C1263V18-300BZI CY7C1263V18-300BZXC CY7C1263V18-300BZXI CY7C1263V18-333BZC CY7C1263V18-333BZI CY7C1263V18-333BZXC CY7C1263V18-333BZXI CY7C1263V18-375BZC CY7C1263V18-375BZI CY7C1263V18-375BZXC CY7C1263V18-375BZXI CY7C1263V18-400BZC CY7C1263V18-400BZI CY7C1263V18-400BZXC CY7C1263V18-400BZXI CY7C1265V18-333BZC CY7C1261V18-333BZC CY7C1261V18-375BZC CY7C1265V18-375BZC CY7C1261V18-300BZI CY7C1265V18-300BZI CY7C1261V18-400BZI CY7C1265V18-400BZI CY7C1265V18-300BZC CY7C1261V18-300BZC CY7C1265V18-400BZC CY7C1276V18-400BZC CY7C1261V18-400BZC CY7C1276V18-375BZXC
OCR Text	...6v18) 1m x 8 array clk a (19:0) gen. k k control logic address register d [7:0] read add. decode read data reg. rps wps q [7:0] control logi...ii+. the timing for the echo clocks is shown in ?switching character- istics? on page 23 . cq echo ...
Description	36-Mbit QDR?II SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency)
File Size	1,101.64K / 28 Page	View it Online	Download Datasheet

				Cypress Semiconductor
Part No.	CY7C1425KV18-250BZC CY7C1414KV18 CY7C1414KV18-250BZC CY7C1414KV18-250BZXC CY7C1414KV18-333BZC
OCR Text	...rray 2M x 8 Array K K CLK Gen. Control Logic RPS C C CQ DOFF Read Data Reg. 16 VREF WPS NWS[1:0] 8 Control Logic 8 ...II SRAM ........................... 20 Power Up Sequence ..............................................
Description	36-Mbit QDR? II SRAM 2-Word Burst Architecture
File Size	590.54K / 30 Page	View it Online	Download Datasheet

				Cypress Semiconductor
Part No.	CY7C1415KV18 CY7C1415KV18-250BZC CY7C1415KV18-250BZI CY7C1415KV18-250BZXI CY7C1415KV18-250BZXC CY7C1413KV18 CY7C1413KV18-250BZC CY7C1413KV18-250BZXC CY7C1413KV18-250BZXI CY7C1413KV18-300BZC CY7C1413KV18-300BZXC CY7C1413KV18-333BZC CY7C1413KV18-250BZI
OCR Text	...rray 1M x 8 Array K K CLK Gen. Control Logic RPS C C CQ DOFF Read Data Reg. 32 VREF WPS NWS[1:0] 16 Control Logic 16...II SRAM ........................... 21 Power Up Sequence ..............................................
Description	36-Mbit QDR? II SRAM 4-Word Burst Architecture
File Size	642.79K / 33 Page	View it Online	Download Datasheet

				Cypress Semiconductor
Part No.	CY7C1315KV18 CY7C1315KV18-250BZC CY7C1315KV18-250BZXC CY7C1315KV18-250BZXI CY7C1315KV18-300BZC CY7C1313KV18 CY7C1313KV18-250BZC CY7C1313KV18-250BZI CY7C1311KV18 CY7C1313KV18-250BZXI
OCR Text	...y 512 K x 8 Array K K CLK Gen. Control Logic RPS C C CQ DOFF Read Data Reg. 32 VREF WPS NWS[1:0] 16 Control Logic 16...II SRAM ........................... 21 Power Up Sequence ..............................................
Description	18-Mbit QDR? II SRAM Four-Word Burst Architecture
File Size	622.94K / 33 Page	View it Online	Download Datasheet

				Cypress Semiconductor
Part No.	CY7C1265KV18 CY7C1276KV18 CY7C1265KV18-550BZC CY7C1265KV18-400BZC CY7C1265KV18-400BZXC CY7C1265KV18-450BZXC CY7C1263KV18-400BZC CY7C1263KV18-400BZI CY7C1263KV18-500BZXC CY7C1263KV18-550BZI CY7C1261KV18 CY7C1263KV18-550BZXC CY7C1265KV18-550BZXC
OCR Text	...rray 1M x 8 Array K K CLK Gen. Control Logic RPS DOFF Read Data Reg. CQ 32 VREF WPS NWS[1:0] 16 Control Logic 16 ...II+ SRAM ......................... 20 Power Up Sequence ...............................................
Description	36-Mbit QDR? II SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency)
File Size	658.28K / 28 Page	View it Online	Download Datasheet

				Cypress Semiconductor
Part No.	CY7C1245KV18 CY7C1243KV18 CY7C1243KV18-400BZC CY7C1241KV18 CY7C1243KV18-450BZC CY7C1245KV18-450BZC CY7C1245KV18-400BZC CY7C1245KV18-400BZXC CY7C1256KV18
OCR Text	...rray 1M x 8 Array K K CLK Gen. Control Logic RPS DOFF Read Data Reg. CQ 32 VREF WPS NWS[1:0] 16 Control Logic 16 ...II+ SRAM ......................... 20 Power Up Sequence ...............................................
Description	36-Mbit QDR? II SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency)
File Size	630.78K / 28 Page	View it Online	Download Datasheet

				Cypress Semiconductor Corp.
Part No.	CY7C1241V18 CY7C1243V18 CY7C1241V18-300BZC CY7C1241V18-300BZI CY7C1241V18-300BZXC CY7C1241V18-300BZXI CY7C1243V18-300BZI CY7C1245V18-300BZI CY7C1256V18-300BZI CY7C1243V18-300BZC CY7C1245V18-300BZXI CY7C1245V18-300BZXC CY7C1243V18-300BZXI CY7C1243V18-300BZXC CY7C1245V18-300BZC
OCR Text	...y 1M x 8 Array K K CLK Gen. Control Logic RPS DOFF Read Data Reg. 32 Control Logic 16 16 Reg. Reg. 8 Reg. 8 CQ CQ Q[...II+. The timing for the echo clocks is shown in "Switching Characteristics" on page 23. Page 6 of 28...
Description	36-Mbit QDRII SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency) 36兆位的国防评估报告⑩- II SRAM4字突发架构（2.0周期读写延迟
File Size	1,036.02K / 28 Page	View it Online	Download Datasheet

				CYPRESS SEMICONDUCTOR CORP
Part No.	CY7C11481KV18-400BZC
OCR Text	...rite reg write reg clk a (19:0) gen. k k control logic address register read add. decode read data reg. r/w output logic reg. reg. reg. 8 16...ii+ sram ............ ........... .... 20 power up sequence .........................................
Description	1M X 18 DDR SRAM, 0.45 ns, PBGA165
File Size	619.48K / 28 Page	View it Online	Download Datasheet

For gen-ii Found Datasheets File :: 1128 Search Time::2.906ms
Page :: | 1 | 2 | 3 | 4 | <5> | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 |