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ST Microelectronics
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| Part No. |
STM3240G-SK/KEI
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| OCR Text |
...ent , which integrates the arm compilation tools and keil?s debugging software so that users can quickly and easily develop and debug their applications while they run on a target microcontroller. arm compilation tools (rvct) 32 kbyte c... |
| Description |
Keil starter kit for STM32 F4 series microcontrollers (STM32F407IG MCU)
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| File Size |
587.56K /
4 Page |
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Altera Corporation
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| Part No. |
EP910I EP1810 EP910 EP610 EP610I EP910LC-30
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| OCR Text |
...DL)--and waveform design entry, compilation and logic synthesis, simulation and timing analysis, and device programming. The MAX+PLUS II software provides EDIF 2 0 0 and 3 0 0, LPM, VHDL, Verilog HDL, and other interfaces for additional des... |
| Description |
CPLD, EP910 Family, ECMOS Process, 450 Gates, 24 Macro Cells, 24 Reg., 24 User I/Os, 5V Supply, 30 Speed Grade, 44LDCC
The Altera Classic device family offers a solution to high-speed, lowpower logic integration. Fabricated on advanced CMOS technology
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| File Size |
293.93K /
42 Page |
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Altera Corp
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| Part No. |
EP610PC-15
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| OCR Text |
...DL)--and waveform design entry, compilation and logic synthesis, simulation and timing analysis, and device programming. The MAX+PLUS II software provides EDIF 2 0 0 and 3 0 0, LPM, VHDL, Verilog HDL, and other interfaces for additional des... |
| Description |
IC,SIMPLE-EPLD,PAL-TYPE,CMOS,DIP,24PIN,PLASTIC
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| File Size |
311.73K /
42 Page |
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it Online |
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ALTERA
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| Part No. |
EP20K100EQ EP20K100QC EP20K100EQC240-2
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| OCR Text |
...HDL and schematic design entry, compilation and logic synthesis, full simulation and worst-case timing analysis, SignalTap logic analysis, and device configuration. The Quartus II software runs on Windows-based PCs, Sun SPARCstations, and H... |
| Description |
Apex 20KE Device Family (1.8V, LVDS
Apex 20K Device Family (2.5V)
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| File Size |
585.74K /
116 Page |
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it Online |
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Altera
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| Part No. |
EPM7128E EPM7064 EPM7160E EPM7032 MAX7000
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| OCR Text |
...DL)--and waveform design entry, compilation and logic synthesis, simulation and timing analysis, and device programming. The Quartus and MAX+PLUS II software provides EDIF 2 0 0 and 3 0 0, LPM, VHDL, Verilog HDL, and other interfaces for ad... |
| Description |
MAX7000
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| File Size |
1,072.55K /
85 Page |
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it Online |
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Atmel corp
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| Part No. |
ATC20NBSP ATC20
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| OCR Text |
...mpiled Megacell Library enables compilation of megacells for the functions Synchronous RAM, Asynchronous RAM, Asynchronous Dual-port RAM and Synchronous ROM, according to the user's precise requirements. The Atmel megacells can be instanced... |
| Description |
The ATC20 CBIC family is fabricated on a proprietary 0.21 micron five-layer metal CMOS process inten
From old datasheet system
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| File Size |
80.29K /
11 Page |
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it Online |
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Price and Availability
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