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pll-output Datasheet PDF File

For pll-output Found Datasheets File :: 23415 Search Time::1.328ms
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				Analog Devices
Part No.	AD9984A-15
OCR Text	...ps maximum conversion rate low pll clock jitter at 170 msps automatic gain matching automated offset adjustment 2:1 input mux power-dow...output format modes variable output drive strength odd/even field detection external clock input ...
Description	High Performance 10-Bit Display Interface
File Size	530.90K / 44 Page	View it Online	Download Datasheet

				ONSEMI[ON Semiconductor]
Part No.	NBC12439 NBC12439FA NBC12439FAR2 NBC12439FN NBC12439FNR2
OCR Text	PLL Synthesized Clock Generator 50 MHz to 800 MHz http://onsemi.com The NBC12439 is a general purpose, PLL based synthesized clock sour...output divider, where it can be configured to provide division ratios of 1, 2, 4 or 8. The VCO and o...
Description	3.3 V/5 V Programmable PLL Synthesized Clock Generator
File Size	143.17K / 20 Page	View it Online	Download Datasheet

				PHILIPS[Philips Semiconductors]
Part No.	P89C557E4 P89C557E4EBB P89C557E4EFB P83C557E4 P83C557E4EBB P83C557E4EFB P80C557E4EFB P80C557E4 P80C557E4EBB P80C557E4EFB/01
OCR Text	...d oscillator: 3.5 MHz to 16 MHz PLL oscillator with 32 kHz reference and software-selectable system clock frequency Seconds Timer Software enable/disable of ALE output pulse Electromagnetic compatibility improvements Wake-up from Power-down...
Description	P83C557E4/P80C557E4/P89C557E4; Single-chip 8-bit microcontroller
File Size	361.76K / 72 Page	View it Online	Download Datasheet

				Analog Devices
Part No.	AD9980-15
OCR Text	...nversi on rate 9% or less p-p pll clock jitter at 95 msps automated offset adjustm e nt 2:1 input m u x power-down vi a dedicated pi n or serial regis t er 4:4:4, 4: 2:2, an d ddr output f o rmat modes variable output drive strengt...
Description	High Performance 8-Bit Display Interface
File Size	514.64K / 44 Page	View it Online	Download Datasheet

				SIEMENS[Siemens Semiconductor Group] Infineon
Part No.	Q67106-H5157 SDA5649 SDA5649X Q67100-H5156
OCR Text	...utput from sync slicer used for PLL based clock generation. Not connected Data available output active low, when PDC/VPS data is received. Output signaling the presence of the first field active high. Test input; activates test mode when pu...
Description	From old datasheet system Expanded Decoder for Program Delivery Control and Video Program System EPDC / VPS Decoder
File Size	477.76K / 26 Page	View it Online	Download Datasheet

				Analog Devices, Inc.
Part No.	AD9540
OCR Text	...ichip synchronization Dual-mode PLL lock detect 655 MHz CML-mode PECL-compliant driver APPLICATIONS Clocking high performance data conve...output driver with programmable slew rates. External VCO rates up to 2.7 GHz are supported. Extremel...
Description	655 MHz Low Jitter Clock Generator
File Size	476.15K / 32 Page	View it Online	Download Datasheet

				Infineon SIEMENS[Siemens Semiconductor Group]
Part No.	Q67106-H5183 SDA5642-6 SDA5642-6X SDA5642X Q67100-H5182 SDA5642-6XGEG
OCR Text	...utput from sync slicer used for PLL based clock generation. Data available output active low, when VPS data is received. Output signaling the presence of the first field active high. Test input; activates test mode when pulled high. Connect...
Description	PDC Decoder VPS-Decoder VPS Decoder From old datasheet system
File Size	684.24K / 27 Page	View it Online	Download Datasheet

				SIEMENS[Siemens Semiconductor Group]
Part No.	Q67106-H6423 Q-67106-H6514 PMB2306 PMB2306R PMB2306T Q67100-H6423
OCR Text	PLL-Frequency Synthesizer PMB2306R/PMB2306T Version 2.2 Data Sheet 02.97 T2306-0V22-D1-7600 30%530%7 5HYLVLRQ +LVWRU\ Previous Versio...output by current sources 30% 5 * Synchronous programming of the counters (n-, n/a-, r-counters) and...
Description	PLL-Frequency Synthesizer PMB2306R/PMB2306T Version 2.2
File Size	757.92K / 35 Page	View it Online	Download Datasheet

				ETC[ETC]
Part No.	QL8050 QL8150 QL8250 QL8025 QL8325
OCR Text	...VTTL, LVCMOS, LVCMOS18, PCI, PLL Embedded RAM Blocks Embeded Computational Units PLL GTL+, SSTL2, and SSTL3 Independent I/O Ba...Output, Output Enable (OE) )LJXUH (FOLSVH,, %ORFN 'LDJUDP 4XLFN/RJLF &RUSRUDWLRQ Prelimina...
Description	LOW POWER FPGA COMBINING PERFORMANCE DENSITY AND EMBEDED RAM
File Size	442.48K / 49 Page	View it Online	Download Datasheet

				Maxim Integrated Products, Inc. MAXIM - Dallas Semiconductor
Part No.	MAX9486 MAX9486EUG
OCR Text	...se-lock loops (PLLs). The first PLL uses a voltage-controlled crystal oscillator (VCXO). The second PLL is a frequency multiplier. With the two PLLs, the MAX9486 generates the output frequency at 35.328MHz. In addition, this device generate...
Description	8kHz Reference Clock Synthesizer with Multiple Outputs at 35.328MHz 35.328 MHz, OTHER CLOCK GENERATOR, PDSO24
File Size	543.96K / 8 Page	View it Online	Download Datasheet

For pll-output Found Datasheets File :: 23415 Search Time::1.328ms
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