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Cypress Semiconductor, Corp.
CYPRESS SEMICONDUCTOR CORP
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| Part No. |
CY7C1543KV18-400BZC CY7C1545KV18-450BZXI
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| OCR Text |
...rt. deselecti ng the write port ignores d [x:0] . nws 0 , nws 1 , input- synchronous nibble write select 0, 1 ? active low (cy7c1541kv18 only) . sampled on the rising edge of the k and k clocks when write operations are active . us... |
| Description |
Sync SRAM; Architecture: QDR-II , 4 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V 4M X 18 QDR SRAM, 0.45 ns, PBGA165
2M X 36 QDR SRAM, 0.45 ns, PBGA165
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| File Size |
562.79K /
28 Page |
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Cypress Semiconductor, Corp.
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| Part No. |
CY7C1314BV18-167BZXC
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| OCR Text |
...rt. de selecting the write port ignores d [x:0] . nws 0 , nws 1 nibble write select 0, 1 ? active low (cy7c1310bv18 only) . sampled on the rising edge of the k and k clocks during write operations. used to select which nibble is writ... |
| Description |
18-Mbit QDRII SRAM 2 Word Burst Architecture 512K X 36 QDR SRAM, 0.5 ns, PBGA165
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| File Size |
418.24K /
29 Page |
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it Online |
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Cypress Semiconductor, Corp.
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| Part No. |
CY7C1412BV18-250BZC
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| OCR Text |
...rt. de selecting the write port ignores d [x:0] . bws 0 , bws 1 , bws 2 , bws 3 input- synchronous byte write select 0, 1, 2, and 3 ? active low . sampled on the rising edge of the k and k clocks during write operations. used to sele... |
| Description |
2MX18 QDR-II BURST 2 SRAM 2M X 18 QDR SRAM, 0.45 ns, PBGA165
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| File Size |
885.74K /
24 Page |
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it Online |
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Cypress Semiconductor, Corp.
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| Part No. |
CY7C1277V18-300BZC CY7C1266V18-300BZXC CY7C1266V18-333BZC CY7C1266V18-333BZXC
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| OCR Text |
...electing a nibble write select ignores the corresponding nibble of data and not written into the device. bws 0 , bws 1 , bws 2 , bws 3 input- synchronous byte write select 0, 1, 2, and 3, active low . sampled on the rising edge of the k... |
| Description |
36-Mbit DDR-II SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency) 4M X 9 DDR SRAM, 0.45 ns, PBGA165
36-Mbit DDR-II SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency) 4M X 8 DDR SRAM, 0.45 ns, PBGA165
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| File Size |
449.61K /
27 Page |
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it Online |
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ST Microelectronics
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| Part No. |
MK50H28PLCC52 MK50H28Q25
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| OCR Text |
...s only as a bus master. mk50h28 ignores the bm lines when it is a bus slave. byte selection is done as outlined in the following table. bm1 bm0 type of transfer low low entire word low high upper byte (dal<15:08>) high low lower byte (dal<0... |
| Description |
MULTI LOGICAL LINK FRAME RELAY CONTROLLER
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| File Size |
431.87K /
64 Page |
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it Online |
Download Datasheet |
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