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Electronic Theatre Controls, Inc.
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| Part No. |
WV3EG128M72EFSR335D3SG
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| OCR Text |
...double-data-rate architecture ddr266 and ddr333 ? jedec design speci? cations bi-directional data strobes (dqs) differential clock inputs (ck & ck#) programmable read latency 2,2,5 (clock) programmable burst length (2,4,8) prog... |
| Description |
1GB - 128Mx72 DDR SDRAM REGISTERED w/PLL, FBGA 1GB 128Mx72 DDR SDRAM的注册瓦锁相环,FBGA封装
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| File Size |
323.98K /
13 Page |
View
it Online |
Download Datasheet
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Xilinx, Inc.
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| Part No. |
W3EG72256MS133AJD3SG
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| OCR Text |
...ata-rate architecture ddr200, ddr266 and ddr333: ? jedec design speci? cations bi-directional data strobes (dqs) differential clock inputs (ck & ck#) programmable read latency 2,2.5 (clock) programmable burst length (2,4,8) pr... |
| Description |
2GB-256Mx72 DDR SDRAM REGISTERED ECC w/PLL 2GB 256Mx72 ECC的DDR SDRAM的注册瓦锁相
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| File Size |
310.29K /
14 Page |
View
it Online |
Download Datasheet
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SAMSUNG
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| Part No. |
K4H561638F
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| OCR Text |
... Max Freq. B3(DDR333@CL=2.5) AA(ddr266@CL=2) A2(ddr266@CL=2) B0(ddr266@CL=2.5) B3(DDR333@CL=2.5) AA(ddr266@CL=2) A2(ddr266@CL=2) B0(ddr266@CL=2.5) SSTL2 66pin TSOP II SSTL2 66pin TSOP II Interface Package
Operating Frequencies
B3(DDR333... |
| Description |
DDR SDRAM 256Mb F-die
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| File Size |
203.41K /
23 Page |
View
it Online |
Download Datasheet
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Price and Availability
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