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Silicon Laboratories, Inc.
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| Part No. |
SL23EP08ZC-1HT SL23EP08ZI-1HT SL23EP08SC-2T SL23EP08SI-1 SL23EP08SI-1H SL23EP08SI-1HT
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| OCR Text |
...d low power zero delay buffer (zdb) designed to produce up to nine (9) clock outputs from one (1) reference input clock, for high speed clock distribution applications. the product has an on - chip pll and a feedback pin (fbk) wh... |
| Description |
23EP SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 4.40 MM, ROHS COMPLIANT, TSSOP-16
23EP SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 0.150 INCH, ROHS COMPLIANT, SOIC-16
Low Jitter and Skew 10 to 220 MHz Zero Delay Buffer
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| File Size |
170.45K /
15 Page |
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it Online |
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Silicon Laboratories, Inc.
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| Part No. |
SL2309ZI-1HT
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| OCR Text |
...d low power zero delay buffer (zdb) designed to produce up to nine (9) clock outputs from one (1) reference input clock, for high speed clock distribution applications. the product has an on - chip pll which locks to the input clock... |
| Description |
2309 SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 4.40 MM, ROHS COMPLIANT, TSSOP-16
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| File Size |
133.19K /
12 Page |
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it Online |
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Silicon Laboratories, Inc.
HIROSE ELECTRIC Co., Ltd.
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| Part No. |
SL23EP08SC-2T SL23EP08SC-2H
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| OCR Text |
... 220 mhz zero dela y buffer ( zdb ) key features ? 10 to 220 mhz operating frequency range ? low output clock skew: 70ps-typ ? low output clock jitter: <200ps ? low part-to-part output skew: 150 ps-typ ? 3.3v to 2.5v ... |
| Description |
23EP SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 0.150 INCH, ROHS COMPLIANT,SOIC-16
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| File Size |
239.03K /
18 Page |
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it Online |
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CYPRESS SEMICONDUCTOR CORP
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| Part No. |
W194-70G
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| OCR Text |
...e same time as the input to the zdb. in order to achieve this, layout must compensate for trace length between the zdb and the target devices. the method of compensation is described below. external feedback is the trait that allows for thi... |
| Description |
Miscellaneous Clock Generator
W19 SERIES, PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8
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| File Size |
103.20K /
6 Page |
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it Online |
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Cypress Semiconductor, Corp.
CYPRESS SEMICONDUCTOR CORP
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| Part No. |
CY2509ZXC-1 CY25010 CY250911 CY2510ZXC-1 CY2510ZXC-1T
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| OCR Text |
... same time as the input to the zdb. in order to achieve this, layout must compensate for trace length between the zdb and the target devices. the method of compensation is described below. external feedback is the trait that allows for... |
| Description |
Spread Aware(TM), Ten/Eleven Output Zero Delay Buffer; Voltage (V): 3.3 V; Frequency Range: 40 MHz to 140 MHz; Outputs: 10; Operating Range: 0 to 70 C 2509 SERIES, PLL BASED CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO24
Spread Aware? Ten/Eleven Output Zero Delay Buffer
Spread Aware(TM), Ten/Eleven Output Zero Delay Buffer; Voltage (V): 3.3 V; Frequency Range: 40 MHz to 140 MHz; Outputs: 11; Operating Range: 0 to 70 C 2510 SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO24
Spread Aware(TM), Ten/Eleven Output Zero Delay Buffer; Voltage (V): 3.3 V; Frequency Range: 40 MHz to 140 MHz; Outputs: 11; Operating Range: 0 to 70 C
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| File Size |
201.39K /
11 Page |
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Cypress Semiconductor Corp.
Cypress Semiconductor, Corp.
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| Part No. |
CY23020LFI-3T
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| OCR Text |
... (pll)-based zero delay buffer (zdb) designed for high- speed clock distribution applications. the device features a guaranteed ttb window specifying all occurrences of output clocks with respect to the input reference clock across variatio... |
| Description |
10-output, 400-MHz LVPECL Zero Delay Buffer 23020 SERIES, PLL BASED CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), QCC48
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| File Size |
109.87K /
9 Page |
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it Online |
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Price and Availability
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