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Cypress Semiconductor Corp.
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| Part No. |
CY7C375i
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| OCR Text |
...O81 i/O80 GND i/O30 i/O31 CLK0 /i0 VCCiO GND CLK1 /i1 i/O32 i/O33 i/O34 i/O35 i/O36 i/O37 i/O38 i/O39 GND i/O40 i/O41 i/O42 i/O43 i/O44 i/O45 i/O46 i/O47 VCCiO 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 ... |
| Description |
UltraLogic 128-Macrocell Flash CPLD(超逻辑128-宏单元闪速CPLD) UltraLogic 128宏单元CPLD的闪光（超逻辑128 -宏单元闪速的CPLD
UltraLogic 128-Macrocell Flash CPLD(超逻辑28-宏单元闪速CPLD)
From old datasheet system
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| File Size |
262.76K /
16 Page |
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it Online |
Download Datasheet
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Integrated Circuit Syst...
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| Part No. |
iCS950223
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| OCR Text |
.... 2 = f e r i f e r i * 5 = h o i0 6 @ v 1 7 . 0 00 s m h o 0 5 % 1 5 7 4 = r r a m 2 3 . 2 = f e r i f e r i * 5 = h o i0 5 @ v 9 5 . 0 01 s m h o 0 6 % 1 5 7 4 = r r a m 2 3 . 2 = f e r i f e r i * 6 = h o i0 6 2 / v 5 8 . 0 01 s m h o 0 ... |
| Description |
Programmable Timing Control Hub for P4
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| File Size |
211.33K /
24 Page |
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it Online |
Download Datasheet |
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ZARLINK[Zarlink Semiconductor Inc]
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| Part No. |
SP5524 SP5524SKGMPAS SP5524SKG SP5524SKGMPAD
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| OCR Text |
...ocked. Bits 3, 4 and 5 (i2, i1, i0) show the status of the i/O Ports P0, P2 and P3 respectively. A logic 0 indicates a low level and a logic 1 a high level. if the ports are to be used as inputs they should be programmed to a high impedance... |
| Description |
Bidirectional i2C Bus Controlled Synthesiser
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| File Size |
189.21K /
10 Page |
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it Online |
Download Datasheet |
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Price and Availability
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