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UPD16 SA22A DS2760X F7N50 5RM487 BAY7305 ML9XX43 97179
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  asychronous latched Datasheet PDF File

For asychronous latched Found Datasheets File :: 24    Search Time::3.922ms    
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    AV9148F-03

Integrated Circuit Systems
Part No. AV9148F-03
OCR Text ... timing diagram cpu_stop# is an asychronous input to the clock synthesizer. it is used to turn off the cpu clocks for low power operation. cpu_stop# is synchronized by the ics9148-03 . the minimum that the cpu clock is enabled (cpu_stop# h...
Description Frequency generator and integrated buffers for Pentium/PRO
File Size 559.75K  /  12 Page

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    ICS
Part No. ICS9148-49
OCR Text ...Timing Diagram CPUS_TOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPUCLKs for low power operation. CPU_STOP# is synchronized by the ICS9148-49. All other clocks will continue to run while the CPUCLKs clo...
Description BX Main Clock, 2 Chip Clock, Supports 66.6 - 100MHz
From old datasheet system
File Size 360.16K  /  9 Page

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    ICS952301 ICS952301YG-T

Integrated Circuit Systems
ICS
Part No. ICS952301 ICS952301YG-T
OCR Text ... Timing Diagram CPUSTOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPUCLKs for low power operation. CPU_STOP# is synchronized by the ICS952301. The minimum that the CPUCLK is enabled (CPU_STOP# high pulse...
Description Frequency Timing Generator for Transmeta Systems
File Size 577.81K  /  12 Page

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For asychronous latched Found Datasheets File :: 24    Search Time::3.922ms    
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