| |
|
 |
Cypress
|
| Part No. |
CY7C1314V18-167BZC
|
| OCR Text |
...0v18 ? 2m x 8 cy7c1312v18 ? 1m x 18 cy7c1314v18 ? 512k x 36 functional description the cy7c1310v18/cy7c1312v18/cy7c1314v18 are 1.8v synchronous pipelined srams, equipped with qdr ? -ii archi- tecture. qdr tm -ii architecture consists ... |
| Description |
18-Mb SRAM two-word burst architecture, 167MHz
|
| File Size |
446.03K /
25 Page |
 View
it Online |
Download Datasheet
|
| |
|
|
Cypress
|
| Part No. |
CY7C1387DV25
|
| OCR Text |
1m x 18) pipelined dcd sync sram cy7c1386dv25 cy7c1387dv25 cypress semiconductor corporation ? 3901 north first street ? san jose , ca 951...512k x 36) address register adv clk burst counter and logic clr q1 q0 adsc bw b bw a ce 1 dq b, dqp... |
| Description |
18-Mbit (512k x 36/1m x 18) Pipelined DCD Sync SRAM
|
| File Size |
458.84K /
32 Page |
View
it Online |
Download Datasheet |
| |
|
|
Cypress
|
| Part No. |
CY7C1526V18-167BZC CY7C1511V18-167BZC CY7C1513V18-167BZC CY7C1513V18-200BZC
|
| OCR Text |
...gic block diagram (cy7c1513v18) 1m x 18 array clk a (19:0) gen. k k control logic address register d [17:0] read add. decode read data reg. ...512k x 36 array clk a (18:0) gen. k k control logic address register d [35:0] read add. decode read ... |
| Description |
72 Mbit QDR-II SRAM 4-word burst architecture. Speed 167 MHz.
72 Mbit QDR-II SRAM 4-word burst architecture. Speed 200 MHz.
|
| File Size |
371.30K /
24 Page |
View
it Online |
Download Datasheet |
|
Price and Availability
|
