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Advanced Micro Devices, Inc.
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| Part No. |
PALCE29MA16
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| OCR Text |
...lled clocks can also be used in asychronous application. v 1
0 preset reset s2 s3 1 1
1 0
0 1
0 0 s4 s5 common i/ oe (pin) indi...latched, or combinatorial input. the palce29ma16 has a dedicated clk/ le pin and one individual clk... |
| Description |
24-Pin EE CMOS Programmable Array Logic
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| File Size |
295.17K /
25 Page |
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it Online |
Download Datasheet
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ICST[Integrated Circuit Systems]
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| Part No. |
ICS9248-95
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| OCR Text |
...Timing Diagram
CLK_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPU clocks for low power operation. CLK_STOP# is synchronized by the ICS9248-95. The minimum that the CPU clock is enabled (CPU_STOP# hig... |
| Description |
Frequency Generator & Integrated Buffers for PENTIUM/ProTM
Single Chip MVP4 Clock
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| File Size |
296.48K /
16 Page |
View
it Online |
Download Datasheet |
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ATMEL Corporation
Atmel, Corp.
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| Part No. |
ATF22LV10C-15PC ATF22LV10C-10JC ATF22LV10C-10JI ATF22LV10C-10PC ATF22LV10C-10PI ATF22LV10C-10SC ATF22LV10C-10SI ATF22LV10C-10SU ATF22LV10C-10XC ATF22LV10C-10XI ATF22LV10C-10XU ATF22LV10C-15JC ATF22LV10C-15JI ATF22LV10C-15PI ATF22LV10C-15SC ATF22LV10C-10JU ATF22LV10C-10PU ATF22LV10C-15XI ATF22LV10C-15XC ATF22LV10C-15SI ATF22LV10C-10SJ ATF22LV10C-10XJ ATF22LV10C-10JL
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| OCR Text |
...ynchronous preset 10 10 ns t aw asychronous reset width 8 8 ns t ar asychronous reset recovery time 6 6 ns t spr synchronous preset to clock...latched and held. therefore, all registered and combinatorial output data remain valid. any outputs ... |
| Description |
High-performance Electrically Erasable Programmable Logic Device
10NS, SOIC, IND TEMP, GREEN(EPLD) FLASH PLD, 10 ns, PDSO24
FLASH PLD, 10 ns, PQCC28
High Performance E2 PLD
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| File Size |
1,744.84K /
19 Page |
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it Online |
Download Datasheet |
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Atmel Corp
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| Part No. |
ATF22LV10CNBSP ATF22LV10C
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| OCR Text |
... Setup Time, Synchronous Preset asychronous Reset Width asychronous Reset Recovery Time Synchronous Preset to Clock Recovery Time 1. See ord...latched and held. Therefore, all registered and combinatorial output data remain valid. Any outputs ... |
| Description |
500 gate low voltage electrically erasable PLD, 24 pins
From old datasheet system
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| File Size |
223.13K /
14 Page |
View
it Online |
Download Datasheet |
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ICS
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| Part No. |
ICS9148-49
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| OCR Text |
...Timing Diagram
CPUS_TOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPUCLKs for low power operation. CPU_STOP# is synchronized by the ICS9148-49. All other clocks will continue to run while the CPUCLKs clo... |
| Description |
BX Main Clock, 2 Chip Clock, Supports 66.6 - 100MHz
From old datasheet system
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| File Size |
360.16K /
9 Page |
View
it Online |
Download Datasheet |
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For
asychronous latched Found Datasheets File :: 20 Search Time::1.313ms
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