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IDT
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| Part No. |
IDT72V51353 IDT72V51343 IDT72V51333
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| OCR Text |
...EAD CONTROL
WADEN FSTR WRADD wen WCLK
6
RADEN ESTR
7
Q0
RDADD REN RCLK OE
x9, x18 DATA IN
Din
Qout
x9, x18 DATA OUT
WRITE FLAGS READ FLAGS
FF PAF PAFn
8
OV PAE PAEn
Q7
8
5940 drw01
IDT and the IDT... |
| Description |
3.3V MULTI-QUEUE FLOW-CONTROL DEVICES
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| File Size |
436.97K /
49 Page |
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IDT
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| Part No. |
IDT72V36110
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| OCR Text |
... only.
D0 -Dn (x36, x18 or x9) wen WCLK/WR LD SEN
*
INPUT REGISTER
OFFSET REGISTER
FF/IR PAF EF/OR PAE HF FWFT/SI PFM FSEL0 FSEL1
*ASYW
WRITE CONTROL LOGIC RAM ARRAY 65,536 x 36 131,072 x 36 WRITE POINTER
FLAG LOGIC
REA... |
| Description |
3.3 VOLT HIGH-DENSITY SUPERSYNC II? 36-BIT FIFO
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| File Size |
442.15K /
47 Page |
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it Online |
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PCA Electronics, Inc. Integrated Device Technology Inc
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| Part No. |
IDT72230L10TP IDT72220L10TP
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| OCR Text |
...(WCLK), and a Write Enable pin (wen). Data is written into the Synchronous FIFO on every clock when wen is asserted. The output port is controlled by another clock pin (RCLK) and a Read Enable pin (REN). The Read Clock can be tied to the Wr... |
| Description |
x8 Synchronous FIFO x8同步FIFO From old datasheet system FIFO,2KX8,SYNCHRONOUS,CMOS,DIP,28PIN,PLASTIC
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| File Size |
86.40K /
11 Page |
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it Online |
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INTEGRATED DEVICE TECHNOLOGY INC
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| Part No. |
IDT72V13081L15PFGI
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| OCR Text |
... (wclk) and write enable pin ( wen ). data is written into the multimedia fifo on every rising clock edge when the write enable pin is asserted. the output port is controlled by another clock pin (rclk) and read enable pin ( ren ). the rea... |
| Description |
2K X 8 OTHER FIFO, 10 ns, PQFP32
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| File Size |
121.79K /
9 Page |
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Zarlink
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| Part No. |
PDSP16256A PDSP16256
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| OCR Text |
...s returned low. C15:0 A7:0 CCS
wen CS BYTE EPROM
Description
F31:0 FEN
DFEN
SWAP FRUN
DCLR
16-bit coefficient input bus. In the Byte mode of operation, C15:8 have alternative uses as explained in the text. Coefficient addre... |
| Description |
Programmable FIR Filter
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| File Size |
196.27K /
25 Page |
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it Online |
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