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Elpida Memory, Inc.
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| Part No. |
D4564841G5 UPD4564441 UPD4564163 UPD4564841
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| OCR Text |
...m-bit synchronous dram 4-bank, lvttl data sheet document no. e0149n10 (ver.1.0) (previous no. m12621ejcv0ds00) date published augu...3) ? automatic precharge and controlled precharge ? cbr (auto) refresh and self refresh ? 4,... |
| Description |
64M-bit Synchronous DRAM 4-bank, LVTTL
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| File Size |
902.22K /
85 Page |
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it Online |
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Integrated Device Techn...
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| Part No. |
ICS854110I
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| OCR Text |
... table 3a for fu nction. lvcmos/lvttl interface levels. 3 clk0 input non-inverting clock/data input 0. 4 nclk0 input inverting differential clock input 0. 5, 9, 25 gnd power power supply ground. 6 clk1 input non-inverting clock/data input 1... |
| Description |
2.5V Differential LVDS Clock Buffer
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| File Size |
761.61K /
21 Page |
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it Online |
Download Datasheet |
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Integrated Device Techn...
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| Part No. |
ICS854104I
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| OCR Text |
...q0 outputs. see table 3. lvcmos/lvttl interface levels. 2 oe1 input pullup output enable pin for q1, nq1 outputs. see table 3. lvcmos/lvttl interface levels. 3 oe2 input pullup output enable pin for q2, nq2 outputs. see table 3. lvcmos/lvtt... |
| Description |
Low Skew, 1-to-4, Differential-to-LVDS Fanout Buffer
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| File Size |
284.54K /
15 Page |
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it Online |
Download Datasheet |
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Integrated Device Techn...
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| Part No. |
5V49EE903NLGI 5V49EE903NLGI8 5V49EE903PGGI 5V49EE903PGGI8
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| OCR Text |
.../o standards: ? outputs - 3.3 v lvttl/ lvcmos ? inputs - 3.3 v lvttl/ lvcmos programmable slew rate control programmable loop bandwidth programmable output inversion to reduce bimodal jitter redundant clock inputs with auto and manual s... |
| Description |
EEPROM PROGRAMMABLE CLOCK GENERATOR
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| File Size |
339.91K /
31 Page |
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it Online |
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