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GSI Technology, Inc.
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| Part No. |
GS8160Z36BGT-250IV GS8160Z18BGT-200IV GS8160Z18BT-200IV GS8160Z36BGT-150IV GS8160Z36BT-150IV GS8160Z18BT-150IV GS8160Z18BGT-250IV GS8160Z36BT-250IV GS8160Z36BGT-200IV GS8160Z18BT-250IV GS8160Z36BT-250V GS8160Z36BT-200V GS8160Z36BGT-250V GS8160Z36BT-150V GS8160Z36BGT-200V GS8160Z36BGT-150V 60Z18BGT-150V 60Z18BGT-150IV
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| OCR Text |
..., nobl or other pipelined read/double late write or flow through read/ single late write srams, allow u tilization of all available bus ba...cycle and then released to the output dr ivers at the next rising edge of clock. the gs8160zxxbt-... |
| Description |
18Mb Pipelined and Flow Through Synchronous NBT SRAM 512K X 36 ZBT SRAM, 5.5 ns, PQFP100
18Mb Pipelined and Flow Through Synchronous NBT SRAM 1M X 18 ZBT SRAM, 6.5 ns, PQFP100
18Mb Pipelined and Flow Through Synchronous NBT SRAM 512K X 36 ZBT SRAM, 7.5 ns, PQFP100
18Mb Pipelined and Flow Through Synchronous NBT SRAM 1M X 18 ZBT SRAM, 7.5 ns, PQFP100
18Mb Pipelined and Flow Through Synchronous NBT SRAM 1M X 18 ZBT SRAM, 5.5 ns, PQFP100
18Mb Pipelined and Flow Through Synchronous NBT SRAM 512K X 36 ZBT SRAM, 6.5 ns, PQFP100
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| File Size |
441.74K /
22 Page |
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it Online |
Download Datasheet
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GSI Technology, Inc.
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| Part No. |
GS8160Z36T-166T
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| OCR Text |
..., nobl or other pipelined read/double late write or flow through read/single late write srams, allow utilization of all available bus ban...cycle and then released to the output driv ers at the next rising edge of clock. the gs8160z18/36... |
| Description |
512K X 36 ZBT SRAM, 7 ns, PQFP100 TQFP-100
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| File Size |
437.15K /
24 Page |
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it Online |
Download Datasheet |
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Samsung Electronic
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| Part No. |
M312L3223BT0
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| OCR Text |
...ng M312L3223BT0 is 32M bit x 72 Double Data Rate SDRAM high density memory modules based on first generation of 256Mb DDR SDRAM respectively...cycle control with the use of system clock. Data I/O transactions are possible on both edges of DQS.... |
| Description |
M312L3223BT0 DDR SDRAM 184pin DIMM Data Sheet
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| File Size |
94.58K /
15 Page |
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it Online |
Download Datasheet |
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Maxim Integrated Products, Inc.
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| Part No. |
DS1643
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| OCR Text |
...ly. the rtc clock registers are double buffered to avoid access of incorrect data that can occur during clock up- date cycles. the double b...cycle. ce or we must return inactive for a minimum of t wr prior to the initiation of another re... |
| Description |
Nonvolatile Timekeeping RAM(非易失性计时RAM)
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| File Size |
132.65K /
13 Page |
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it Online |
Download Datasheet |
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Maxim Integrated Products, Inc.
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| Part No. |
DS1644
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| OCR Text |
...y. the rtc clock registers are double buffered to avoid access of incorrect data that can occur during clock update cycles. the double buf...cycle. ce or we must return inactive for a minimum of t wr prior to the initiation of another read... |
| Description |
Nonvolatile Timekeeping RAM(非易失性计时RAM)
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| File Size |
131.95K /
12 Page |
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it Online |
Download Datasheet |
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Maxim Integrated Products, Inc.
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| Part No. |
DS1646
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| OCR Text |
...y. the rtc clock registers are double buff- ered to avoid access of incorrect data that can occur during clock update cycles. the double b...cycle. ce or we must return inactive for a minimum of t wr prior to the initiation of another re... |
| Description |
Nonvolatile Timekeeping RAM(非易失性计时RAM)
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| File Size |
131.71K /
12 Page |
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it Online |
Download Datasheet |
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Westcode Semiconductors
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| Part No. |
R1271NS12X
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| OCR Text |
...icable for t j below 25c. 2) double side cooled, single phase; 50hz, 180 half-sinewave. 3) single side cooled, single phase; 50hz, 180 ...cycle lines the 100% duty cycle is represented on all the ratings by a straight line. other duties ... |
| Description |
(R1271NS10x / R1271NS12x) Distributed Gate Thyristor
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| File Size |
295.67K /
12 Page |
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it Online |
Download Datasheet |
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