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Infineon
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| Part No. |
SAE81C80A SAE81C80
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| OCR Text |
...tates when a memory location is concurrently accessed by two processors, even if they write simultaneously to the same memory location. Depending on the internal state of the access control and the actual physical sequence, the value one of... |
| Description |
CMOS Dual-Port RAM
From old datasheet system
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| File Size |
700.77K /
27 Page |
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XILINX[Xilinx, Inc]
Xilinx, Inc.
XILINX INC
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| Part No. |
XC9536-5VQ44C XC9536 XC9536-10 XC9536-10CS48C XC9536-10PC44C XC9536-10VQ44C XC9536-5PC44I XC9536-5CS XC9536-7VQ XC9536-15V XC9536-15VQ44C XC9536-7PC44C XC9536-7VQ44C XC9536-6PC44C XC9536-6PC44I XC9536-5CS48C XC9536-15PC44I XC9536-15VQ44I 9536 XC9536-15CS48C XC9536-15CS48I XC9536-5CS48I XC9536-10CS48I XC9536-15PC44C XC9536-6VQ44I XC9536-7 XC9536-5PC44C XC9536-7VQ44I XC9536-10PC44I XC9536-10VQ44I XC9536-15 XC9536-5 XC9536-5VQ44I XC9536-6 XC9536-6CS48C XC9536-6CS48I XC9536-6VQ44C XC9536-7CS48C XC9536-7PC44I XC9536-7CS48I XC9536-SERIES
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| OCR Text |
...ramming of more than one XC9500 concurrently Available in 44-pin PLCC, 44-pin VQFP, and 48-pin CSP packages
Power Management
Power dissipation can be reduced in the XC9536 by configuring macrocells to standard or low-power modes of oper... |
| Description |
XC9536: 5V ISP CPLD Family
Product Specification
From old datasheet system
XC9536 In-System Programmable CPLD FLASH PLD, 5 ns, PBGA48
XC9536 In-System Programmable CPLD XC9536在系统可编程的CPLD
XC9536 In-System Programmable CPLD FLASH PLD, 10 ns, PQCC44
XC9536 In-System Programmable CPLD FLASH PLD, 15 ns, PQCC44
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| File Size |
52.72K /
7 Page |
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XILINX
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| Part No. |
XC9572
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| OCR Text |
...ramming of more than one XC9500 concurrently Available in 44-pin PLCC, 84-pin PLCC, 100-pin PQFP, and 100-pin TQFP packages
Description
The XC9572 is a high-performance CPLD providing advanced in-system programming and test capabilities... |
| Description |
In-System Programmable CPLD
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| File Size |
75.10K /
8 Page |
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Cypress
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| Part No. |
CY7C1031 CY7C1032 7C1031 CY7C1031-8JCT CY7C1032-10JCT
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| OCR Text |
...red if ADSP or ADSC is asserted concurrently with CS. Note that ADSP has no effect on ADV if CS is HIGH. Chip select. This signal is sampled by the rising edge of CLK. If CS is HIGH and ADSC is LOW, the SRAM is deselected. If CS is LOW and ... |
| Description |
64K x 18 Synchronous Cache RAM
From old datasheet system
64K x 18 SynchronousCache RAM
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| File Size |
229.64K /
12 Page |
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QLogic
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| Part No. |
ISP2200A
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| OCR Text |
... supports SCSI and IP protocols concurrently.
s s s s s s s s s s
Software Drivers
The ISP2200A supports a host software interface similar to the QLogic parallel SCSI and FC-AL processor family. Existing ISP2100A software drivers for... |
| Description |
Controller Miscellaneous
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| File Size |
58.24K /
4 Page |
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Fujitsu
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| Part No. |
MB84VA2006-10 MB84VA2007-10
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| OCR Text |
...y combination of sectors can be concurrently erased. Also supports full chip erase. * Boot Code Sector Architecture MB84VA2006: Top sector MB84VA2007: Bottom sector * Embedded EraseTM Algorithms Automatically pre-programs and erases the chi... |
| Description |
8M (x 8/x 16) FLASH MEMORY & 1M (x 8) STATIC RAM
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| File Size |
245.60K /
29 Page |
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Price and Availability
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