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Cypress
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| Part No. |
CY7C1526V18-167BZC CY7C1511V18-167BZC CY7C1513V18-167BZC CY7C1513V18-200BZC
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| OCR Text |
...1v18) 2m x 8 array clk a (20:0) gen. k k control logic address register d [7:0] read add. decode read data reg. rps wps q [7:0] control logi...ii comp letely eliminates the need to ?turn-around? the data bus and avoids any possible data conten... |
| Description |
72 Mbit QDR-II SRAM 4-word burst architecture. Speed 167 MHz.
72 Mbit QDR-II SRAM 4-word burst architecture. Speed 200 MHz.
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| File Size |
371.30K /
24 Page |
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Download Datasheet
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List of Unclassifed Man...
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| Part No. |
B7016G24V4H B7016G24W4H GT24-B7016
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| OCR Text |
.../ ecc memory ? (2) fh/hl pci-e (gen.2) x16 slots (w/ x8 link) ? (3) gbe lan ? (4) hot-swap sas hdds w/ raid 0/1/1e support (b7016g24w4h only) ? (4) hot-swap sata-ii hdds w/ raid 0/1/10/5 support ? onboard bmc w/ ikvm support ? (1) eps1u hi... |
| Description |
Best 1U dual-socket SMP server implementation for HPC and enterprise virtualization applications
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| File Size |
802.92K /
2 Page |
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it Online |
Download Datasheet |
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Cypress Semiconductor, Corp.
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| Part No. |
CY7C1423JV18-250BZXC
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| OCR Text |
...jv18) 2m x 8 array clk a (20:0) gen. k k control logic address register d [7:0] read add. decode read data reg. ld q [7:0] reg. reg. reg. 8 ...ii. in the single clock mode, cq is generated with respect to k. the timings for the echo clocks ... |
| Description |
36-Mbit DDR-II SIO SRAM 2-Word Burst Architecture; Architecture: DDR-II SIO, 2 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V 2M X 18 DDR SRAM, 0.45 ns, PBGA165
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| File Size |
914.73K /
27 Page |
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it Online |
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