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CYPRESS SEMICONDUCTOR CORP
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| Part No. |
CY39100Z208B-83NI CY39100Z208B-200NC CY39100V256A-125BBC CY39100V388-83MGC 100Z484B-125BBC
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| OCR Text |
...lvttl, 3.3v pci, sstl2 (i-ii), sstl3 (i-ii), hstl (i-iv), and gtl+ compatible with nobl ? , zbt ? , and qdr ? srams programmable slew rate control on each i/o pin user-programmable bus hold capability on each i/o pin fully pci co... |
| Description |
LOADABLE PLD, 15 ns, PQFP208
LOADABLE PLD, 7.5 ns, PQFP208
LOADABLE PLD, 10 ns, PBGA256
LOADABLE PLD, 15 ns, PBGA388
LOADABLE PLD, 10 ns, PBGA484
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| File Size |
1,174.66K /
56 Page |
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it Online |
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quicklogic
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| Part No. |
QL6325E QL6325E_DS
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| OCR Text |
...LVCMOS18, PCI, GTL+, SSTL2, and sstl3 Eight independent I/O banks Three register configurations: Input, Output, and Output Enable
Fabric
PLL
Embedded RAM Blocks
PLL
(c) 2005 QuickLogic Corporation
www.quicklogic.com * *
*... |
| Description |
FPGA Combining Performance, Density, and Embedded RAM
From old datasheet system
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| File Size |
687.14K /
56 Page |
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it Online |
Download Datasheet |
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CYPRESS SEMICONDUCTOR CORP
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| Part No. |
CY39200Z676-167MBC
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| OCR Text |
...lvttl, 3.3v pci, sstl2 (i-ii), sstl3 (i-ii), hstl (i-iv), and gtl+ compatible with nobl ? , zbt ? , and qdr ? srams programmable slew rate control on each i/o pin user-programmable bus hold capability on each i/o pin fully pci com... |
| Description |
LOADABLE PLD, 8.5 ns, PBGA676
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| File Size |
1,173.95K /
57 Page |
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it Online |
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Agere Systems
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| Part No. |
OR4E2 OR4E4 OR4E6 OR4E10
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| OCR Text |
... Single-ended: GTL, GTL+, PECL, sstl3/2 (class I & II), HSTL (Class I, III, IV), zero-bus turn-around (ZBT*), and double data rate (DDR). -- Double-ended: LDVS, bused-LVDS, LVPECL. -- Customer defined: Ability to substitute arbitrary standa... |
| Description |
Field-Programmable Gate Arrays
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| File Size |
1,412.01K /
124 Page |
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it Online |
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Lattice Semiconductor
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| Part No. |
ORSPI4
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| OCR Text |
...LVTTL, LVCMOS, GTL, GTL+, PECL, sstl3/2, HSTL, ZBT, DDR, LVDS, bused-LVDS, and LVPECL 1036-pin ftSBGA package provides enough FPGA user I/Os (498) for 4 full-duplex XGMII interfaces, 4 full-duplex PL-3 interfaces, etc; a 40% smaller 1156-pi... |
| Description |
Dual SPI4 Interface and High-Speed SERDES FPSC
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| File Size |
1,147.30K /
263 Page |
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it Online |
Download Datasheet |
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QUICKLOGIC CORP
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| Part No. |
QL902M200-2PSN544C
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| OCR Text |
...lvcmos18, pci, gtl+, sstl2, and sstl3 ! independent i/o banks capable of support ing multiple standards in one device ! i/o register configurations: in put, output, output enable (oe) advanced clock network multiple dedicated low skew cl... |
| Description |
FPGA, 2016 CLBS, 533000 GATES, PBGA544
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| File Size |
703.84K /
106 Page |
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it Online |
Download Datasheet |
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Price and Availability
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