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pll-output Datasheet PDF File

For pll-output Found Datasheets File :: 22835 Search Time::1.782ms
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				Sony Corporation
Part No.	CXD2507AQ
OCR Text	...g functions. Features * Digital PLL * EFM frame sync protection * SEC strategy-based error correction * Subcode demodulation, CRC checking ...output 16K RAM * Double-speed playback capability * New microcomputer interface circuit Absolute M...
Description	From old datasheet system CD Digital Signal Processor
File Size	372.72K / 38 Page	View it Online	Download Datasheet

				SONY[Sony Corporation]
Part No.	CXD2508AQ CXD2508AR
OCR Text	...C. Features DSP block * Digital PLL * EFM frame sync protection * SEC strategy-based error correction * Subcode demodulation, CRC checking ...output 16K RAM * Double-speed playback capability * New microcomputer interface circuit Digital fi...
Description	From old datasheet system CD Digital Signal Processor
File Size	854.77K / 49 Page	View it Online	Download Datasheet

				Sony Corporation
Part No.	CXD2529Q
OCR Text	... PCO 38 CLTV 42 PWM PWM Digital PLL Sub Code Processor Digital OUT 3rd-Order Noise Shaper FOK 23 SEIN 13 CNIN 14 Servo Auto Sequencer ...output pin; normally open. Master clock frequency-divider output. Selects and outputs XTAI x 1, x 1/...
Description	From old datasheet system CD Digital Signal Processor
File Size	671.86K / 64 Page	View it Online	Download Datasheet

				Sony Corporation
Part No.	CXD3068Q
OCR Text	...al, is generated by the digital PLL. * EFM data demodulation * Enhanced EFM frame sync signal protection * Refined super strategy-based powe...output from a new CPU interface * Servo auto sequencer * Fine search performs track jumps with high ...
Description	CD Digital Signal Processor with Built-in Digital Servo
File Size	1,217.71K / 134 Page	View it Online	Download Datasheet

				Integrated Device Technology, Inc.
Part No.	IDT23S09E-1PGI IDT23S09E-1HPG IDT23S09E-1HDC IDT23S09E-1DC IDT23S09E-1DCI IDT23S09E-1HDCI IDT23S09E-1HPGI
OCR Text	...s a high-speed phase-lock loop (PLL) clock buffer, designed to address high-speed clock distribution applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range o...
Description	3.3V ZERO DELAY CLOCK BUFFER, SPREAD SPECTRUM COMPATIBLE 23S SERIES, PLL BASED CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 3.3V ZERO DELAY CLOCK BUFFER, SPREAD SPECTRUM COMPATIBLE 3.3零延迟时钟缓冲器，扩频兼
File Size	55.15K / 8 Page	View it Online	Download Datasheet

				Integrated Circuit Systems TE Connectivity, Ltd.
Part No.	ICS8422002I-01 ICS8422002AGI-01T
OCR Text	...ace levels. Selects between the PLL and TEST_CLK as input to the dividers. When Pulldown LOW, selects PLL (PLL Enable). When HIGH, deselects...output, XTAL_IN is the input. Pulldown LVCMOS/LVTTL clock input. Selects between cr ystal or TEST_CL...
Description	FEMTOCLOCKSCRYSTAL-TO-LVHSTL FREQUENCY SYNTHESIZER FEMTOCLOCKS⑩晶体对LVHSTL频率合成
File Size	188.70K / 13 Page	View it Online	Download Datasheet

				SONY[Sony Corporation]
Part No.	CXL1506 CXL1506M CXL1506N
OCR Text	...al circuits * Built-in tripling PLL circuit * For PAL signals * 1 input and 2 outputs (Outputs for both 1H and 2H delays) Absolute Maximum R...Output circuit S/H 1bit 1698bits Output circuit S/H 1bit Bias circuit Clamp circuit CCD (1698b...
Description	CMOS-CCD 1H/2H Delay Line for PAL
File Size	168.57K / 12 Page	View it Online	Download Datasheet

				SONY[Sony Corporation]
Part No.	CXL5502M CXL5502N CXL5502P
OCR Text	...-pass filter. The ICs contain a PLL circuit (quadruple progression). Features * Single power supply (5V) * Low power consumption 95mW (Typ.)...Output circuit (S/H 1bit) Clamp circuit I/O control Timing circuit Bias circuit (A) Bias ci...
Description	CMOS-CCD 1H Delay Line for NTSC
File Size	185.05K / 13 Page	View it Online	Download Datasheet

				SONY[Sony Corporation]
Part No.	CXL5505M CXL5505P
OCR Text	...l circuits * Built-in quadruple PLL circuit Functions * 1130-bit CCD register * Clock driver * Auto-bias circuit * Input clamp circuit * Sam...Output circuit (S/H 1bit) Clamp circuit Bias circuit (B) 7 VDD 14 13 AB 12 11 1...
Description	CMOS-CCD 1H Delay Line for PAL
File Size	124.17K / 9 Page	View it Online	Download Datasheet

				SONY[Sony Corporation]
Part No.	CXL5509M CXL5509P
OCR Text	...l circuits * Built-in quadruple PLL circuit * For NTSC signals * 1 input and 2 outputs (Outputs for both 1H and 2H delays) Functions * 906-b...Output circuit (S/H 1bit) 1816bit Output circuit (S/H 1bit) Bias circuit 1 2 3 4 5 ...
Description	CMOS-CCD 1H/2H Delay Line for NTSC
File Size	154.66K / 12 Page	View it Online	Download Datasheet

For pll-output Found Datasheets File :: 22835 Search Time::1.782ms
Page :: | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | <12> | 13 | 14 | 15 |