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PMC[PMC-Sierra, Inc]
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| Part No. |
PM7382-PI PM7382
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| OCR Text |
...6 HIGH-LEVEL DATA LINK CONTROL (hdlc) PROTOCOL.........36 RECEIVE CHANNEL ASSIGNER ................................................37 8.3.1 ...dma CONTROLLER ...................................................44 8.5.1 8.5.2 DATA STRUCTURES ...... |
| Description |
FRAME ENGINE AND DATA LINK MANAGER 32P256
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| File Size |
2,473.56K /
330 Page |
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it Online |
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Motorola
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| Part No. |
XPC855TZP80D4
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| OCR Text |
...pecially programmed devices) -- hdlc/SDLC (all channels supported at 2 Mbps) -- hdlc bus (implements an hdlc-based local area network (LAN)) -- Asynchronous hdlc to support point-to-point protocol (PPP)
MPC860 Family Hardware Specification... |
| Description |
(XPC860 Series) Family Hardware Specifications
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| File Size |
515.41K /
80 Page |
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it Online |
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Motorola
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| Part No. |
MPC852T
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| OCR Text |
...rting full 10-Mbps operation -- hdlc/SDLC -- hdlc bus (implements an hdlc-based local area network (LAN)) -- Universal asynchronous receiver...dma Channels
MII
SCC3
SCC4
SMC1
SPI
Serial Interface (NMSI)
Figure 1. MPC852T B... |
| Description |
COMMUNICATIONS CONTROLLER
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| File Size |
1,012.58K /
80 Page |
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it Online |
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ZILOG[Zilog, Inc.]
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| Part No. |
Z16C3010VSC Z16C30
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| OCR Text |
...Character Sync Mode for Receive hdlc/SDLC Mode with Eight-Bit Address Compare; Extended Address Field Option; 16- or 32-Bit CRC; Programmabl...dma Interface with Separate Request and Acknowledge for Each Receiver and Transmitter Channel Load C... |
| Description |
CMOS USC Universal Controller
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| File Size |
734.30K /
86 Page |
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it Online |
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Motorola
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| Part No. |
MPC8260A
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| OCR Text |
...nal connections - Transparent - hdlc--Up to T3 rates (clear channel) -- Two multichannel controllers (MCCs) - Each MCC handles 128 serial, f...dma channels for the following transfers: - PCI-to-60x to 60x-to-PCI - 60x-to-PCI to PCI-to-60x - PC... |
| Description |
Micro Processor
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| File Size |
329.91K /
48 Page |
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it Online |
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Motorola
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| Part No. |
MPC8260E
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| OCR Text |
...nal connections - Transparent - hdlc--Up to T3 rates (clear channel) -- Two multichannel controllers (MCCs) - Each MCC handles 128 serial, f...dma outputs
Output specifications are measured from the 50% level of the rising edge of CLKIN to ... |
| Description |
Micro Processor
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| File Size |
335.42K /
36 Page |
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it Online |
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