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Cypress Semiconductor, Corp.
CYPRESS SEMICONDUCTOR CORP
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| Part No. |
CY2509ZXC-1 CY25010 CY250911 CY2510ZXC-1 CY2510ZXC-1T
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| OCR Text |
... same time as the input to the zdb. in order to achieve this, layout must compensate for trace length between the zdb and the target devices. the method of compensation is described below. external feedback is the trait that allows for... |
| Description |
Spread Aware(TM), Ten/Eleven Output Zero Delay Buffer; Voltage (V): 3.3 V; Frequency Range: 40 MHz to 140 MHz; Outputs: 10; Operating Range: 0 to 70 C 2509 SERIES, PLL BASED CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO24
Spread Aware? Ten/Eleven Output Zero Delay Buffer
Spread Aware(TM), Ten/Eleven Output Zero Delay Buffer; Voltage (V): 3.3 V; Frequency Range: 40 MHz to 140 MHz; Outputs: 11; Operating Range: 0 to 70 C 2510 SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO24
Spread Aware(TM), Ten/Eleven Output Zero Delay Buffer; Voltage (V): 3.3 V; Frequency Range: 40 MHz to 140 MHz; Outputs: 11; Operating Range: 0 to 70 C
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| File Size |
201.39K /
11 Page |
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it Online |
Download Datasheet
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Integrated Device Technology, Inc.
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| Part No. |
ICS9DB801CFLFT
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| OCR Text |
... select bypass(fan-out) or pll (zdb) mode 0 = bypass mode, 1= pll mode 23 sclk input clock pin of smbus circuitry, 5v tolerant. 24 sdata i/o data pin for smbus circuitry, 5v tolerant.
idt tm /ics tm eight output differential buffer f... |
| Description |
Eight Output Differential Buffer for PCI Express (50-200MHz) 9DB SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48
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| File Size |
207.52K /
19 Page |
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it Online |
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Cypress Semiconductor, Corp.
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| Part No. |
CY2302SC-1
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| OCR Text |
...e same time as the input to the zdb. in order to achieve this, layout must compensate for trace length between the zdb and the target devices. the method of compensation is described as follows. external feedback is the trait t hat allows ... |
| Description |
Frequency Multiplier and Zero Delay Buffer 2302 SERIES, PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8
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| File Size |
184.34K /
7 Page |
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it Online |
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Cypress Semiconductor, Corp.
CYPRESS SEMICONDUCTOR CORP
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| Part No. |
CY2302SXI-1T
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| OCR Text |
... same time as the input to the zdb. in order to achieve this, layout must compensate for trace length between the zdb and the target devices. the method of compensation is described as follows. external feedback is the trait that allow... |
| Description |
Frequency Multiplier and Zero Delay Buffer; Voltage (V): 3.3/5.0 V; Frequency Range: 10 MHz to 133 MHz; Outputs: 2; Operating Range: -40 to 85 C 23S SERIES, PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8
Frequency Multiplier and Zero Delay Buffer; Voltage (V): 3.3/5.0 V; Frequency Range: 10 MHz to 133 MHz; Outputs: 2; Operating Range: -40 to 85 C
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| File Size |
363.89K /
9 Page |
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it Online |
Download Datasheet |
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