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Samsung
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| Part No. |
S5N8951 S5N8947 S5N8950
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| OCR Text |
...y supports ATM Adaptation Layer Five (AAL5) Segmentation And Reassembly -- Segments and reassembles data up to 70Mbps -- A glueless UTOPIA level 1/2 interface is supprted (for receiving and transmitting ATM cells with SAR, it is a standard ... |
| Description |
1 Port ADSL Transceiver W/PCI
ARM7TDMI 72MHz,H/W SAR,UTOPIA L1/2,USB,2 Ethernet MAC
Full Rate(G.dmt/G.lite) dmt Transceiver for CO/CPE
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| File Size |
802.05K /
108 Page |
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it Online |
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Integrated Device Technology, Inc.
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| Part No. |
89HPES6T5ZABC 89HPES6T5ZABCG
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| OCR Text |
...six 2.5gbps pci express lanes ? five switch ports ? upstream port is x2 ? downstream ports are x1 ? low-latency cut-through switch architect...layer mux / demux transaction layer data link layer (port 0) (port 2) serdes phy logical layer mux /... |
| Description |
6-Lane 5-Port PCI Express Switch
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| File Size |
262.32K /
28 Page |
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it Online |
Download Datasheet |
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Xilinx Inc
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| Part No. |
XC5202-3PC84C
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| OCR Text |
...), and control logic. There are five independent inputs and three outputs to each LC. The independence of the inputs and outputs allows the ...layer, freeing the placement software to pack user logic optimally with minimal routing restrictions... |
| Description |
FPGA,64-CELL,CMOS,LDCC,84PIN,PLASTIC
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| File Size |
516.09K /
73 Page |
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it Online |
Download Datasheet |
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pmc
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| Part No. |
1990444
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| OCR Text |
...ACKAGING
* Provides a standard five signal P1149.1 JTAG test port for boundary scan board test purposes. * Implemented in low power, 0.18 micron, 1.5 V CMOS technology with 2.5 V embedded DRAM, 2.5 V external SRAM interface, and 3.3 V exte... |
| Description |
From old datasheet system
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| File Size |
95.45K /
2 Page |
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it Online |
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Price and Availability
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