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Integrated Device Technology, Inc.
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| Part No. |
MPC9993FA
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| OCR Text |
...rs both input clk signals. upon detec tion of a failure (clk stuck high or low for at least 1 period), the inp_bad fo r that clk will be latched (h). if that clk is the primary clock, the idcs will switch to the good secondary clock and ... |
| Description |
IC PLL/IDCS PLL CLK DVR 32-LQFP 9993 SERIES, PLL BASED CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32
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| File Size |
339.09K /
10 Page |
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