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AMIS
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| Part No. |
FS6128-07
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| OCR Text |
...LL is a standard frequency- and phaselocked loop architecture. The PLL multiplies the reference oscillator frequency to the desired output frequency by a ratio of integers. The frequency multiplication is exact with a zero synthesis error (... |
| Description |
PLL clock generator IC with VCXO
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| File Size |
52.17K /
7 Page |
 View
it Online |
Download Datasheet
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ZARLINK
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| Part No. |
GP2010IG
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| OCR Text |
...CTOR
POWER-ON RESET 1.400GHz phaselocked LOOP
SIGN O/P LATCH POWER CONTROL
(13)
SIGN TTL O/P
PLL REF I/P 10MHz (REF 2)
(24)
PLL REFERENCE OSCILLATOR
MAG O/P LATCH
(12)
MAG TTL O/P
(25)
REF 1 I/P
(FOR USE WIT... |
| Description |
GP2010 - GPS Receiver RF Front End
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| File Size |
185.82K /
24 Page |
View
it Online |
Download Datasheet |
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MAXIM - Dallas Semiconductor
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| Part No. |
MAX3874
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| OCR Text |
...nce clock, the fully integrated phaselocked loop (PLL) recovers a synchronous clock signal from the serial NRZ data input. The input data is then retimed by this recovered clock, providing a clean data output. An additional serial input (SL... |
| Description |
2.488Gbps/2.667Gbps Clock and Data Recovery with Limiting Amplifier
From old datasheet system
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| File Size |
460.54K /
13 Page |
View
it Online |
Download Datasheet |
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MAXIM - Dallas Semiconductor
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| Part No. |
MAX3876
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| OCR Text |
... consists of a fully integrated phaselocked loop (PLL), input amplifier, data retiming block, and CML output buffer (Figure 3). The PLL consists of a phase/frequency detector (PFD), a loop filter, and a voltage-controlled oscillator (VCO). ... |
| Description |
2.5Gbps, Low-Power, 3.3V Clock-Recovery and Data-Retiming IC
From old datasheet system
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| File Size |
933.60K /
10 Page |
View
it Online |
Download Datasheet |
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Price and Availability
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